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Message-ID: <CAJF2gTQrfGyitzi7yhcs1dedG9NH2wnieoLu78SUNSaRiyL9dg@mail.gmail.com>
Date: Sat, 20 May 2023 09:16:24 +0800
From: Guo Ren <guoren@...nel.org>
To: Palmer Dabbelt <palmer@...belt.com>
Cc: jszhang@...nel.org, tglx@...utronix.de,
Marc Zyngier <maz@...nel.org>, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
Paul Walmsley <paul.walmsley@...ive.com>,
aou@...s.berkeley.edu, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org,
frank.li@...o.com, wefu@...hat.com, uwu@...nowy.me
Subject: Re: [PATCH v2 9/9] riscv: defconfig: enable T-HEAD SoC
Acked-by: Guo Ren <guoren@...nel.org>
On Sat, May 20, 2023 at 4:56 AM Palmer Dabbelt <palmer@...belt.com> wrote:
>
> On Thu, 18 May 2023 11:45:41 PDT (-0700), jszhang@...nel.org wrote:
> > Enable T-HEAD SoC config in defconfig to allow the default
> > upstream kernel to boot on Sipeed Lichee Pi 4A board.
> >
> > Signed-off-by: Jisheng Zhang <jszhang@...nel.org>
> > ---
> > arch/riscv/configs/defconfig | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> > index d98d6e90b2b8..109e4b5b003c 100644
> > --- a/arch/riscv/configs/defconfig
> > +++ b/arch/riscv/configs/defconfig
> > @@ -27,6 +27,7 @@ CONFIG_EXPERT=y
> > CONFIG_PROFILING=y
> > CONFIG_SOC_MICROCHIP_POLARFIRE=y
> > CONFIG_ARCH_RENESAS=y
> > +CONFIG_ARCH_THEAD=y
> > CONFIG_SOC_SIFIVE=y
> > CONFIG_SOC_STARFIVE=y
> > CONFIG_ARCH_SUNXI=y
>
> Acked-by: Palmer Dabbelt <palmer@...osinc.com>
--
Best Regards
Guo Ren
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