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Message-ID: <20230522161158.GA3330346@hirez.programming.kicks-ass.net>
Date: Mon, 22 May 2023 18:11:58 +0200
From: Peter Zijlstra <peterz@...radead.org>
To: Feng Tang <feng.tang@...el.com>
Cc: Thomas Gleixner <tglx@...utronix.de>,
Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
Dave Hansen <dave.hansen@...el.com>,
"H . Peter Anvin" <hpa@...or.com>, paulmck@...nel.org,
rui.zhang@...el.com, x86@...nel.org, linux-kernel@...r.kernel.org,
bin.gao@...el.com
Subject: Re: [PATCH RFC] x86/tsc: Make recalibration default on for
TSC_KNOWN_FREQ cases
On Mon, May 22, 2023 at 11:20:15PM +0800, Feng Tang wrote:
> And I don't understand the commit log: "On Intel GOLDMONT Atom SoC
> TSC is the only reliable clocksource. We mark TSC reliable to avoid
> watchdog on it."
>
> Clearly the Denventon I found today has both HPET and ACPI_PM timer:
>
> [root@...0 ~]# grep . /sys/devices/system/clocksource/clocksource0/*
> /sys/devices/system/clocksource/clocksource0/available_clocksource:tsc hpet acpi_pm
> /sys/devices/system/clocksource/clocksource0/current_clocksource:tsc
>
> The lscpu info is:
>
> Architecture: x86_64
> CPU op-mode(s): 32-bit, 64-bit
> Address sizes: 39 bits physical, 48 bits virtual
> Byte Order: Little Endian
> CPU(s): 12
> On-line CPU(s) list: 0-11
> Vendor ID: GenuineIntel
> BIOS Vendor ID: Intel(R) Corporation
> Model name: Intel(R) Atom(TM) CPU C3850 @ 2.10GHz
> BIOS Model name: Intel(R) Atom(TM) CPU C3850 @ 2.10GHz CPU @ 2.1GHz
> BIOS CPU family: 43
> CPU family: 6
> Model: 95
> Thread(s) per core: 1
> Core(s) per socket: 12
> Socket(s): 1
> Stepping: 1
>
> Maybe this cpu model (0x5F) has been used by some type of platforms
> which has met the false alarm watchdog issue.
It has them; but they are not *reliable*.
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