linux-kernel - Re: [PATCH v3 2/2] riscv: Add Zawrs support for spinlocks

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20230522-karaoke-reproduce-be1bb503b49c@spud>
Date:   Mon, 22 May 2023 18:43:14 +0100
From:   Conor Dooley <conor@...nel.org>
To:     Heiko Stuebner <heiko@...ech.de>
Cc:     linux-riscv@...ts.infradead.org, palmer@...belt.com,
        paul.walmsley@...ive.com, linux-kernel@...r.kernel.org,
        christoph.muellner@...ll.eu, David.Laight@...lab.com,
        Heiko Stuebner <heiko.stuebner@...ll.eu>
Subject: Re: [PATCH v3 2/2] riscv: Add Zawrs support for spinlocks

Hey Heiko,

On Sun, May 21, 2023 at 01:47:15PM +0200, Heiko Stuebner wrote:
> From: Christoph Müllner <christoph.muellner@...ll.eu>
> 
> The current RISC-V code uses the generic ticket lock implementation,
> that calls the macros smp_cond_load_relaxed() and smp_cond_load_acquire().
> Currently, RISC-V uses the generic implementation of these macros.
> This patch introduces a RISC-V specific implementation, of these
> macros, that peels off the first loop iteration and modifies the waiting
> loop such, that it is possible to use the WRS.STO instruction of the Zawrs
> ISA extension to stall the CPU.
> 
> The resulting implementation of smp_cond_load_*() will only work for
> 32-bit or 64-bit types for RV64 and 32-bit types for RV32.
> This is caused by the restrictions of the LR instruction (RISC-V only
> has LR.W and LR.D). Compiler assertions guard this new restriction.
> 
> This patch uses the existing RISC-V ISA extension framework
> to detect the presence of Zawrs at run-time.
> If available a NOP instruction will be replaced by WRS.NTO or WRS.STO.
> 
> The whole mechanism is gated by Kconfig setting, which defaults to Y.
> 
> The Zawrs specification can be found here:
> https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc
> 
> Signed-off-by: Christoph Müllner <christoph.muellner@...ll.eu>
> [rebase, update to review comments]
> Signed-off-by: Heiko Stuebner <heiko.stuebner@...ll.eu>

I do intend actually reviewing these two, but busy this week with dt
stuff! In the interim, got some build complaints..

gcc-13 & clang-16 allmodconfig:
kernel/rcu/rcuscale.c:819:3: warning: logical not is only applied to the left hand side of this comparison [-Wlogical-not-parentheses]

k210_nommu_defconfig:
include/linux/atomic/atomic-arch-fallback.h:249:23: error: implicit declaration of function 'smp_load_acquire' [-Werror=implicit-function-declaration]
include/linux/atomic/atomic-arch-fallback.h:265:17: error: implicit declaration of function 'smp_store_release' [-Werror=implicit-function-declaration]

Thanks,
Conor.

Download attachment "signature.asc" of type "application/pgp-signature" (229 bytes)