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Message-ID: <7fabb62d-0483-1298-c6ce-1f37313faa67@quicinc.com>
Date: Mon, 22 May 2023 11:03:11 -0700
From: Jessica Zhang <quic_jesszhan@...cinc.com>
To: Marijn Suijten <marijn.suijten@...ainline.org>
CC: Rob Clark <robdclark@...il.com>,
Abhinav Kumar <quic_abhinavk@...cinc.com>,
Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
Sean Paul <sean@...rly.run>, David Airlie <airlied@...il.com>,
Daniel Vetter <daniel@...ll.ch>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
<linux-arm-msm@...r.kernel.org>, <dri-devel@...ts.freedesktop.org>,
<freedreno@...ts.freedesktop.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v3 3/5] drm/msm/dpu: Add DPU_INTF_DATA_COMPRESS feature
flag
On 5/19/2023 2:34 PM, Marijn Suijten wrote:
> On 2023-05-19 14:17:28, Jessica Zhang wrote:
>> Add DATA_COMPRESS feature flag to DPU INTF block.
>>
>> In DPU 7.x and later, DSC/DCE enablement registers have been moved from
>> PINGPONG to INTF.
>>
>> Reviewed-by: Marijn Suijten <marijn.suijten@...ainline.org>
>> Signed-off-by: Jessica Zhang <quic_jesszhan@...cinc.com>
>> ---
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +-
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 ++
>> 2 files changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> index 7944481d0a33..c74051906d05 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> @@ -104,7 +104,7 @@
>> #define INTF_SC7180_MASK \
>> (BIT(DPU_INTF_INPUT_CTRL) | BIT(DPU_INTF_TE) | BIT(DPU_INTF_STATUS_SUPPORTED))
>>
>> -#define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN)
>> +#define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN) | BIT(DPU_INTF_DATA_COMPRESS)
>
> We should really wrap these in parenthesis at some point.
Hi Marijn,
Acked.
Thanks,
Jessica Zhang
>
>>
>> #define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \
>> BIT(DPU_WB_UBWC) | \
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> index 4eda2cc847ef..01c65f940f2a 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> @@ -185,6 +185,7 @@ enum {
>> * @DPU_DATA_HCTL_EN Allows data to be transferred at different rate
>> * than video timing
>> * @DPU_INTF_STATUS_SUPPORTED INTF block has INTF_STATUS register
>> + * @DPU_INTF_DATA_COMPRESS INTF block has DATA_COMPRESS register
>> * @DPU_INTF_MAX
>> */
>> enum {
>> @@ -192,6 +193,7 @@ enum {
>> DPU_INTF_TE,
>> DPU_DATA_HCTL_EN,
>> DPU_INTF_STATUS_SUPPORTED,
>> + DPU_INTF_DATA_COMPRESS,
>> DPU_INTF_MAX
>> };
>>
>>
>> --
>> 2.40.1
>>
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