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Message-ID: <BYAPR03MB47572F2C65E52ED673238D41B2439@BYAPR03MB4757.namprd03.prod.outlook.com>
Date: Mon, 22 May 2023 23:07:21 +0000
From: Andrew Duggan <aduggan@...aptics.com>
To: Jeffery Miller <jefferymiller@...gle.com>,
Dmitry Torokhov <dmitry.torokhov@...il.com>
CC: Andrew Duggan <andrew@...gan.us>,
Jonathan Denose <jdenose@...omium.org>,
"jdenose@...gle.com" <jdenose@...gle.com>,
Lyude Paul <lyude@...hat.com>,
"loic.poulain@...aro.org" <loic.poulain@...aro.org>,
"benjamin.tissoires@...hat.com" <benjamin.tissoires@...hat.com>,
Jonathan Cameron <Jonathan.Cameron@...wei.com>,
Maximilian Luz <luzmaximilian@...il.com>,
Miguel Ojeda <ojeda@...nel.org>,
Uwe Kleine-König
<u.kleine-koenig@...gutronix.de>,
"linux-input@...r.kernel.org" <linux-input@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Vincent Huang <Vincent.huang@...synaptics.com>
Subject: RE: [PATCH] Input: synaptics-rmi4 - retry reading SMBus version on
resume
> From: Jeffery Miller <jefferymiller@...gle.com>
> Sent: Friday, May 12, 2023 12:37
> To: Dmitry Torokhov <dmitry.torokhov@...il.com>
> Cc: Andrew Duggan <andrew@...gan.us>; Jonathan Denose
> <jdenose@...omium.org>; jdenose@...gle.com; Lyude Paul
> <lyude@...hat.com>; loic.poulain@...aro.org;
> benjamin.tissoires@...hat.com; Andrew Duggan
> <aduggan@...aptics.com>; Jonathan Cameron
> <Jonathan.Cameron@...wei.com>; Maximilian Luz
> <luzmaximilian@...il.com>; Miguel Ojeda <ojeda@...nel.org>; Uwe Kleine-
> König <u.kleine-koenig@...gutronix.de>; linux-input@...r.kernel.org;
> linux-kernel@...r.kernel.org
> Subject: Re: [PATCH] Input: synaptics-rmi4 - retry reading SMBus version on
> resume
>
> CAUTION: Email originated externally, do not click links or open attachments
> unless you recognize the sender and know the content is safe.
>
>
> On Wed, May 10, 2023 at 3:06 PM Dmitry Torokhov
> <dmitry.torokhov@...il.com> wrote:
> >
> >
> > I am not really fond of adding random repeats in the code base.
> > Andrew, do you know if the Synaptics device needs certain delay when
> > switching to SMbus mode?
> >
> That's reasonable. It's true this is a sleep to workaround rmi_smbus'
> expectation that
> it is able to successfully read from the i801 i2c smbus addr 0x2c on resume
> when it cannot.
>
> I do not know why the i801 i2c addr 0x2c is not responding on resume.
> Infrequently it won't respond on boot during the initial
> psmouse_smbus_create_companion but that is less noticeable since it will
> stay in ps/2 mode and just lack features.
>
> I do know adding a sleep in-between the psmouse deactivate call and
> rmi_smbus's attempts to read from the 0x2c addr allow it to succeed on this
> machine. I do not know the details as to why however.
Our Windows driver does a 30 ms delay between sending the disable command and trying to communicate over SMBus. I don’t know specifically why this delay is needed, but this is how we handle this case.
>
> I can apply workarounds until the underlying issue can be identified and
> properly resolved.
>
> I can apply patches and provide any sort of debugging or extra information
> that might be useful to anyone familiar with these devices.
>
> The smbus controller in this particular machine is:
> 00:1f.3 SMBus [0c05]: Intel Corporation 8 Series/C220 Series Chipset Family
> SMBus Controller [8086:8c22] (rev 04)
>
> Perhaps there's some way to detect when the addr is available later and have
> it trigger a new probe similar to how psmouse_smbus_notifier is triggered
> when the i801 bus becomes available?
>
> Thank You,
> Jeff
Andrew
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