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Message-ID: <7a9c58b4-e99c-593d-1825-56c698379d09@linaro.org>
Date: Mon, 22 May 2023 11:13:32 +0200
From: neil.armstrong@...aro.org
To: Cong Yang <yangcong5@...qin.corp-partner.google.com>,
sam@...nborg.org, daniel@...ll.ch, dianders@...gle.com,
hsinyi@...gle.com
Cc: dri-devel@...ts.freedesktop.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH] drm/panel: Support for Starry-himax83102-j02 TDDI
MIPI-DSI panel
Hi,
On 19/05/2023 05:23, Cong Yang wrote:
> The Starry-himax83102-j02 panel is a TDDI IC. From the datasheet[1],
> it seems that the touch can communicate successfully only when the RST
> signal is high. Since i2c_hid_core_probe comes after boe_panel_prepare
> let's set the default high for RST at boe_panel_add.
This is a higher level problem, here you basically never set the reset signal to low,
so instead make the reset signal optional and handle the reset elseshere like in a gpio-hog.
>
> [1]: https://github.com/HimaxSoftware/Doc/tree/main/Himax_Chipset_Power_Sequence
PLease update the DT bindings first when introducing a new compatible.
Neil
>
> Signed-off-by: Cong Yang <yangcong5@...qin.corp-partner.google.com>
> ---
> .../gpu/drm/panel/panel-boe-tv101wum-nl6.c | 103 +++++++++++++++++-
> 1 file changed, 102 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
> index 783234ae0f57..0d325fc42bc4 100644
> --- a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
> +++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
> @@ -36,6 +36,7 @@ struct panel_desc {
> const struct panel_init_cmd *init_cmds;
> unsigned int lanes;
> bool discharge_on_disable;
> + int enable_gpio_init_value;
> };
>
> struct boe_panel {
> @@ -75,6 +76,75 @@ struct panel_init_cmd {
> .len = sizeof((char[]){__VA_ARGS__}), \
> .data = (char[]){__VA_ARGS__} }
>
> +static const struct panel_init_cmd starry_himax83102_j02_init_cmd[] = {
> + _INIT_DCS_CMD(0xB9, 0x83, 0x10, 0x21, 0x55, 0x00),
> + _INIT_DCS_CMD(0xB1, 0x2C, 0xB5, 0xB5, 0x31, 0xF1, 0x31, 0xD7, 0x2F, 0x36, 0x36, 0x36, 0x36, 0x1A, 0x8B, 0x11,
> + 0x65, 0x00, 0x88, 0xFA, 0xFF, 0xFF, 0x8F, 0xFF, 0x08, 0x74, 0x33),
> + _INIT_DCS_CMD(0xB2, 0x00, 0x47, 0xB0, 0x80, 0x00, 0x12, 0x72, 0x3C, 0xA3, 0x03, 0x03, 0x00, 0x00, 0x88, 0xF5),
> + _INIT_DCS_CMD(0xB4, 0x76, 0x76, 0x76, 0x76, 0x76, 0x76, 0x63, 0x5C, 0x63, 0x5C, 0x01, 0x9E),
> + _INIT_DCS_CMD(0xE9, 0xCD),
> + _INIT_DCS_CMD(0xBA, 0x84),
> + _INIT_DCS_CMD(0xE9, 0x3F),
> + _INIT_DCS_CMD(0xBC, 0x1B, 0x04),
> + _INIT_DCS_CMD(0xBE, 0x20),
> + _INIT_DCS_CMD(0xBF, 0xFC, 0xC4),
> + _INIT_DCS_CMD(0xC0, 0x36, 0x36, 0x22, 0x11, 0x22, 0xA0, 0x61, 0x08, 0xF5, 0x03),
> + _INIT_DCS_CMD(0xE9, 0xCC),
> + _INIT_DCS_CMD(0xC7, 0x80),
> + _INIT_DCS_CMD(0xE9, 0x3F),
> + _INIT_DCS_CMD(0xE9, 0xC6),
> + _INIT_DCS_CMD(0xC8, 0x97),
> + _INIT_DCS_CMD(0xE9, 0x3F),
> + _INIT_DCS_CMD(0xC9, 0x00, 0x1E, 0x13, 0x88, 0x01),
> + _INIT_DCS_CMD(0xCB, 0x08, 0x13, 0x07, 0x00, 0x0F, 0x33),
> + _INIT_DCS_CMD(0xCC, 0x02),
> + _INIT_DCS_CMD(0xE9, 0xC4),
> + _INIT_DCS_CMD(0xD0, 0x03),
> + _INIT_DCS_CMD(0xE9, 0x3F),
> + _INIT_DCS_CMD(0xD1, 0x37, 0x06, 0x00, 0x02, 0x04, 0x0C, 0xFF),
> + _INIT_DCS_CMD(0xD2, 0x1F, 0x11, 0x1F),
> + _INIT_DCS_CMD(0xD3, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x08, 0x37, 0x47, 0x34, 0x3B, 0x12, 0x12, 0x03,
> + 0x03, 0x32, 0x10, 0x10, 0x00, 0x10, 0x32, 0x10, 0x08, 0x00, 0x08, 0x32, 0x17, 0x94, 0x07, 0x94, 0x00, 0x00),
> + _INIT_DCS_CMD(0xD5, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x19, 0x19, 0x40, 0x40, 0x1A, 0x1A,
> + 0x1B, 0x1B, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x20, 0x21, 0x28, 0x29, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18),
> + _INIT_DCS_CMD(0xD6, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x40, 0x40, 0x19, 0x19, 0x1A, 0x1A,
> + 0x1B, 0x1B, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x29, 0x28, 0x21, 0x20, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18),
> + _INIT_DCS_CMD(0xD8, 0xAA, 0xBA, 0xEA, 0xAA, 0xAA, 0xA0, 0xAA, 0xBA, 0xEA, 0xAA, 0xAA, 0xA0, 0xAA, 0xBA, 0xEA, 0xAA,
> + 0xAA, 0xA0, 0xAA, 0xBA, 0xEA, 0xAA, 0xAA, 0xA0, 0xAA, 0xBA, 0xEA, 0xAA, 0xAA, 0xA0, 0xAA, 0xBA, 0xEA, 0xAA, 0xAA, 0xA0),
> + _INIT_DCS_CMD(0xE0, 0x00, 0x09, 0x14, 0x1E, 0x26, 0x48, 0x61, 0x67, 0x6C, 0x67, 0x7D, 0x7F, 0x80, 0x8B, 0x87, 0x8F, 0x98, 0xAB,
> + 0xAB, 0x55, 0x5C, 0x68, 0x73, 0x00, 0x09, 0x14, 0x1E, 0x26, 0x48, 0x61, 0x67, 0x6C, 0x67, 0x7D, 0x7F, 0x80, 0x8B, 0x87, 0x8F, 0x98, 0xAB, 0xAB, 0x55, 0x5C, 0x68, 0x73),
> + _INIT_DCS_CMD(0xE7, 0x0E, 0x10, 0x10, 0x21, 0x2B, 0x9A, 0x02, 0x54, 0x9A, 0x14, 0x14, 0x00, 0x00, 0x00, 0x00, 0x12, 0x05, 0x02, 0x02, 0x10),
> + _INIT_DCS_CMD(0xBD, 0x01),
> + _INIT_DCS_CMD(0xB1, 0x01, 0xBF, 0x11),
> + _INIT_DCS_CMD(0xCB, 0x86),
> + _INIT_DCS_CMD(0xD2, 0x3C, 0xFA),
> + _INIT_DCS_CMD(0xE9, 0xC5),
> + _INIT_DCS_CMD(0xD3, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0C, 0x01),
> + _INIT_DCS_CMD(0xE9, 0x3F),
> + _INIT_DCS_CMD(0xE7, 0x02, 0x00, 0x28, 0x01, 0x7E, 0x0F, 0x7E, 0x10, 0xA0, 0x00, 0x00, 0x20, 0x40, 0x50, 0x40),
> + _INIT_DCS_CMD(0xBD, 0x02),
> + _INIT_DCS_CMD(0xD8, 0xFF, 0xFF, 0xBF, 0xFE, 0xAA, 0xA0, 0xFF, 0xFF, 0xBF, 0xFE, 0xAA, 0xA0),
> + _INIT_DCS_CMD(0xE7, 0xFE, 0x04, 0xFE, 0x04, 0xFE, 0x04, 0x03, 0x03, 0x03, 0x26, 0x00, 0x26, 0x81, 0x02, 0x40, 0x00, 0x20, 0x9E, 0x04, 0x03, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00),
> + _INIT_DCS_CMD(0xBD, 0x03),
> + _INIT_DCS_CMD(0xE9, 0xC6),
> + _INIT_DCS_CMD(0xB4, 0x03, 0xFF, 0xF8),
> + _INIT_DCS_CMD(0xE9, 0x3F),
> + _INIT_DCS_CMD(0xD8, 0x00, 0x2A, 0xAA, 0xA8, 0x00, 0x00, 0x00, 0x2A, 0xAA, 0xA8, 0x00, 0x00, 0x00, 0x3F, 0xFF, 0xFC, 0x00, 0x00, 0x00, 0x3F, 0xFF, 0xFC, 0x00, 0x00, 0x00, 0x2A, 0xAA, 0xA8, 0x00, 0x00, 0x00, 0x2A, 0xAA, 0xA8, 0x00, 0x00),
> + _INIT_DCS_CMD(0xBD, 0x00),
> + _INIT_DCS_CMD(0xE9, 0xC4),
> + _INIT_DCS_CMD(0xBA, 0x96),
> + _INIT_DCS_CMD(0xE9, 0x3F),
> + _INIT_DCS_CMD(0xBD, 0x01),
> + _INIT_DCS_CMD(0xE9, 0xC5),
> + _INIT_DCS_CMD(0xBA, 0x4F),
> + _INIT_DCS_CMD(0xE9, 0x3F),
> + _INIT_DCS_CMD(0xBD, 0x00),
> + _INIT_DCS_CMD(0x11),
> + _INIT_DELAY_CMD(120),
> + _INIT_DCS_CMD(0x29),
> + {},
> +};
> +
> static const struct panel_init_cmd boe_tv110c9m_init_cmd[] = {
> _INIT_DCS_CMD(0xFF, 0x20),
> _INIT_DCS_CMD(0xFB, 0x01),
> @@ -1620,6 +1690,34 @@ static const struct panel_desc starry_qfh032011_53g_desc = {
> .init_cmds = starry_qfh032011_53g_init_cmd,
> };
>
> +static const struct drm_display_mode starry_himax83102_j02_default_mode = {
> + .clock = 161600,
> + .hdisplay = 1200,
> + .hsync_start = 1200 + 40,
> + .hsync_end = 1200 + 40 + 20,
> + .htotal = 1200 + 40 + 20 + 40,
> + .vdisplay = 1920,
> + .vsync_start = 1920 + 116,
> + .vsync_end = 1920 + 116 + 8,
> + .vtotal = 1920 + 116 + 8 + 12,
> + .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
> +};
> +
> +static const struct panel_desc starry_himax83102_j02_desc = {
> + .modes = &starry_himax83102_j02_default_mode,
> + .bpc = 8,
> + .size = {
> + .width_mm = 141,
> + .height_mm = 226,
> + },
> + .lanes = 4,
> + .format = MIPI_DSI_FMT_RGB888,
> + .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
> + MIPI_DSI_MODE_LPM,
> + .init_cmds = starry_himax83102_j02_init_cmd,
> + .enable_gpio_init_value = 1,
> +};
> +
> static int boe_panel_get_modes(struct drm_panel *panel,
> struct drm_connector *connector)
> {
> @@ -1694,7 +1792,7 @@ static int boe_panel_add(struct boe_panel *boe)
> return PTR_ERR(boe->enable_gpio);
> }
>
> - gpiod_set_value(boe->enable_gpio, 0);
> + gpiod_set_value(boe->enable_gpio, boe->desc->enable_gpio_init_value);
>
> drm_panel_init(&boe->base, dev, &boe_panel_funcs,
> DRM_MODE_CONNECTOR_DSI);
> @@ -1793,6 +1891,9 @@ static const struct of_device_id boe_of_match[] = {
> { .compatible = "starry,2081101qfh032011-53g",
> .data = &starry_qfh032011_53g_desc
> },
> + { .compatible = "starry,himax83102-j02",
> + .data = &starry_himax83102_j02_desc
> + },
> { /* sentinel */ }
> };
> MODULE_DEVICE_TABLE(of, boe_of_match);
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