linux-kernel - [PATCH 0/2] MT8192/95: Set correct MSDCPLL rate

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Message-Id: <20230522093002.75137-1-angelogioacchino.delregno@collabora.com>
Date:   Mon, 22 May 2023 11:30:00 +0200
From:   AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@...labora.com>
To:     matthias.bgg@...il.com
Cc:     robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
        conor+dt@...nel.org, weiyi.lu@...iatek.com, ikjn@...omium.org,
        chun-jie.chen@...iatek.com, tinghan.shen@...iatek.com,
        seiya.wang@...iatek.com, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-mediatek@...ts.infradead.org, kernel@...labora.com,
        AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@...labora.com>
Subject: [PATCH 0/2] MT8192/95: Set correct MSDCPLL rate

This series improves both stability/reliability and performance for
eMMC and SD cards on MT8192 and MT8195, where the PLL may be set at
a sub-optimal rate from the bootloader.

This was tested on MT8192 Asurada Spherion and MT8195 Cherry Tomato
Chromebooks.

AngeloGioacchino Del Regno (2):
  arm64: dts: mediatek: mt8192: Make sure MSDCPLL's rate is 400MHz
  arm64: dts: mediatek: mt8195: Make sure MSDCPLL's rate is 400MHz

 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 ++
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 2 ++
 2 files changed, 4 insertions(+)

-- 
2.40.1