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Message-ID: <20230522105738.2378364-1-andrew.cooper3@citrix.com>
Date: Mon, 22 May 2023 11:57:38 +0100
From: Andrew Cooper <andrew.cooper3@...rix.com>
To: <tglx@...utronix.de>
CC: <James.Bottomley@...senPartnership.com>,
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Jeffrey Hugo <quic_jhugo@...cinc.com>
Subject: [PATCH] x86/apic: Fix use of X{,2}APIC_ENABLE in asm with older binutils
"x86/smpboot: Support parallel startup of secondary CPUs" adds the first use
of X2APIC_ENABLE in assembly, but older binutils don't tolerate the UL suffix.
Switch to using BIT() instead.
Fixes: 7e75178a0950 ("x86/smpboot: Support parallel startup of secondary CPUs")
Reported-by: Jeffrey Hugo <quic_jhugo@...cinc.com>
Tested-by: Jeffrey Hugo <quic_jhugo@...cinc.com>
Signed-off-by: Andrew Cooper <andrew.cooper3@...rix.com>
---
arch/x86/include/asm/apicdef.h | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/x86/include/asm/apicdef.h b/arch/x86/include/asm/apicdef.h
index bf546dfb6e58..4b125e5b3187 100644
--- a/arch/x86/include/asm/apicdef.h
+++ b/arch/x86/include/asm/apicdef.h
@@ -2,6 +2,8 @@
#ifndef _ASM_X86_APICDEF_H
#define _ASM_X86_APICDEF_H
+#include <linux/bits.h>
+
/*
* Constants for various Intel APICs. (local APIC, IOAPIC, etc.)
*
@@ -140,8 +142,8 @@
#define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
#define APIC_BASE_MSR 0x800
#define APIC_X2APIC_ID_MSR 0x802
-#define XAPIC_ENABLE (1UL << 11)
-#define X2APIC_ENABLE (1UL << 10)
+#define XAPIC_ENABLE BIT(11)
+#define X2APIC_ENABLE BIT(10)
#ifdef CONFIG_X86_32
# define MAX_IO_APICS 64
base-commit: 0c7ffa32dbd6b09a87fea4ad1de8b27145dfd9a6
--
2.30.2
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