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Message-ID: <f0fb9e18-4c75-52f2-a192-3aa5b15b2a9d@amd.com>
Date: Tue, 23 May 2023 11:11:48 +0530
From: "Mukunda,Vijendar" <vijendar.mukunda@....com>
To: Pierre-Louis Bossart <pierre-louis.bossart@...ux.intel.com>,
broonie@...nel.org
Cc: alsa-devel@...a-project.org, Basavaraj.Hiregoudar@....com,
Sunil-kumar.Dommati@....com, Mastan.Katragadda@....com,
Arungopal.kondaveeti@....com, mario.limonciello@....com,
Liam Girdwood <lgirdwood@...il.com>,
Jaroslav Kysela <perex@...ex.cz>,
Takashi Iwai <tiwai@...e.com>,
Syed Saba Kareem <Syed.SabaKareem@....com>,
open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH V2 4/9] ASoC: amd: ps: add SoundWire dma driver dma ops
On 22/05/23 22:09, Pierre-Louis Bossart wrote:
>> +union acp_sdw_dma_count {
>> + struct {
>> + u32 low;
>> + u32 high;
>> + } bcount;
> indentation seems off?
will fix it.
>> + u64 bytescount;
>> +};
>> +
>> +struct sdw_dma_ring_buf_reg {
>> + u32 reg_dma_size;
>> + u32 reg_fifo_addr;
>> + u32 reg_fifo_size;
>> + u32 reg_ring_buf_size;
>> + u32 reg_ring_buf_addr;
>> + u32 water_mark_size_reg;
>> + u32 pos_low_reg;
>> + u32 pos_high_reg;
>> };
>> \
>> +static void acp63_config_dma(struct acp_sdw_dma_stream *stream, void __iomem *acp_base,
>> + u32 stream_id)
>> +{
>> + u16 page_idx;
>> + u32 low, high, val;
>> + u32 sdw_dma_pte_offset;
>> + dma_addr_t addr;
>> +
>> + addr = stream->dma_addr;
>> + sdw_dma_pte_offset = SDW_PTE_OFFSET(stream->instance);
>> + val = sdw_dma_pte_offset + (stream_id * 256);
> what is this 256 magic value? use a defined or << 8 ?
This value is used to map to 32-page addresses in scratch memory PTE mapping.
Will use macro for it.
>> +
>> + /* Group Enable */
>> + writel(ACP_SDW_SRAM_PTE_OFFSET | BIT(31), acp_base + ACPAXI2AXI_ATU_BASE_ADDR_GRP_2);
>> + writel(PAGE_SIZE_4K_ENABLE, acp_base + ACPAXI2AXI_ATU_PAGE_SIZE_GRP_2);
>> + for (page_idx = 0; page_idx < stream->num_pages; page_idx++) {
>> + /* Load the low address of page int ACP SRAM through SRBM */
>> + low = lower_32_bits(addr);
>> + high = upper_32_bits(addr);
>> +
>> + writel(low, acp_base + ACP_SCRATCH_REG_0 + val);
>> + high |= BIT(31);
>> + writel(high, acp_base + ACP_SCRATCH_REG_0 + val + 4);
>> + val += 8;
>> + addr += PAGE_SIZE;
>> + }
>> + writel(0x1, acp_base + ACPAXI2AXI_ATU_CTRL);
>> +}
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