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Message-ID: <af25cbbe-bfa9-3d29-360e-e4f932d286c8@baylibre.com>
Date: Tue, 23 May 2023 12:58:32 +0200
From: Alexandre Mergnat <amergnat@...libre.com>
To: AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>, mturquette@...libre.com
Cc: sboyd@...nel.org, matthias.bgg@...il.com, wenst@...omium.org,
chun-jie.chen@...iatek.com, mandyjh.liu@...iatek.com,
miles.chen@...iatek.com, zhaojh329@...il.com,
daniel@...rotopia.org, nfraprado@...labora.com,
rex-bc.chen@...iatek.com, Garmin.Chang@...iatek.com,
msp@...libre.com, yangyingliang@...wei.com,
linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org, kernel@...labora.com
Subject: Re: [PATCH v2 2/2] clk: mediatek: Remove CLK_SET_PARENT from all MSDC
core clocks
On 16/05/2023 15:52, AngeloGioacchino Del Regno wrote:
> Various MSDC core clocks, used for multiple MSDC controller instances,
> share the same parent(s): in order to add parents selection in the
> mtk-sd driver to achieve an accurate clock rate for all modes, remove
> the CLK_SET_RATE_PARENT flag from all MSDC clocks for all SoCs: this
> will make sure that a clk_set_rate() call performed for a clock on
> a secondary controller will not change the rate of a common parent,
> which would result in an overclock or underclock of one of the
> controllers.
>
> Signed-off-by: AngeloGioacchino Del Regno<angelogioacchino.delregno@...labora.com>
> Reviewed-by: Matthias Brugger<matthias.bgg@...il.com>
> Reviewed-by: Markus Schneider-Pargmann<msp@...libre.com>
Tested on mt8365-evk board.
Reviewed-by: Alexandre Mergnat <amergnat@...libre.com>
Tested-by: Alexandre Mergnat <amergnat@...libre.com>
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