linux-kernel - Re: [PATCH v3] phy: cadence: Sierra: Add single link SGMII register configuration

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Message-ID: <a04a6afa-6daf-ca50-9a99-d52764def948@kernel.org>
Date:   Tue, 23 May 2023 15:15:39 +0300
From:   Roger Quadros <rogerq@...nel.org>
To:     Marcin Wierzbicki <mawierzb@...co.com>,
        Vinod Koul <vkoul@...nel.org>,
        Kishon Vijay Abraham I <kishon@...nel.org>,
        Lars-Peter Clausen <lars@...afoo.de>,
        Swapnil Jakhade <sjakhade@...ence.com>,
        Uwe Kleine-König <u.kleine-koenig@...gutronix.de>,
        linux-phy@...ts.infradead.org, linux-kernel@...r.kernel.org
Cc:     xe-linux-external@...co.com, danielwa@...co.com, olicht@...co.com,
        Bartosz Wawrzyniak <bwawrzyn@...co.com>
Subject: Re: [PATCH v3] phy: cadence: Sierra: Add single link SGMII register
 configuration



On 22/05/2023 20:24, Marcin Wierzbicki wrote:
> Add single link SGMII register configuration for no SSC for
> cdns,sierra-phy-t0 compatibility string.
> The configuration is based on Sierra Programmer's Guide and
> validated in Cisco CrayAR SoC.
> 
> Co-developed-by: Bartosz Wawrzyniak <bwawrzyn@...co.com>
> Signed-off-by: Bartosz Wawrzyniak <bwawrzyn@...co.com>
> Signed-off-by: Marcin Wierzbicki <mawierzb@...co.com>
> ---
> v3> - all reported comments were addressed

:)
You should summarize what changes were done.

> - v2: https://lore.kernel.org/lkml/20230508160142.2489365-1-mawierzb@cisco.com/T/#u
> 
> v2
> - rebased version on top of commit 0cfa43ab46b5 ("phy: cadence: Sierra: Add PCIe + SGMII PHY multilink configuration")
> - v1: https://lore.kernel.org/lkml/20230419093008.195094-1-mawierzb@cisco.com/T/
> 
> Regards,
> Marcin

Reviewed-by: Roger Quadros <rogerq@...nel.org>

-- 
cheers,
-roger