linux-kernel - Re: [PATCH v2] dt-bindings: ti-serdes-mux: Add defines for J784S4 SoC

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Message-ID: <d6a7e322-8e60-d4b9-b83f-d364cc3ca133@axentia.se>
Date:   Wed, 24 May 2023 10:21:14 +0200
From:   Peter Rosin <peda@...ntia.se>
To:     Siddharth Vadapalli <s-vadapalli@...com>
Cc:     robh+dt@...nel.org, krzysztof.kozlowski@...aro.org,
        krzysztof.kozlowski+dt@...aro.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        srk@...com
Subject: Re: [PATCH v2] dt-bindings: ti-serdes-mux: Add defines for J784S4 SoC

Hi!

2023-05-16 at 06:40, Siddharth Vadapalli wrote:
> Peter,
> 
> Can this patch please be merged in case of no issues? It applies cleanly on
> linux-next tagged next-20230516.

Sorry for being slow, but this is now finally on its way to linux-next.

Cheers,
Peter

> On 10/03/23 16:46, Siddharth Vadapalli wrote:
>> From: Matt Ranostay <mranostay@...com>
>>
>> There are 4 lanes in the single instance of J784S4 SERDES. Each SERDES
>> lane mux can select up to 4 different IPs. Define all the possible
>> functions.
>>
>> Signed-off-by: Matt Ranostay <mranostay@...com>
>> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
>> Signed-off-by: Siddharth Vadapalli <s-vadapalli@...com>
>> ---
>>
>> Changes from v1:
>> 1. Collect Acked-by tag from Krzysztof Kozlowski.
>> 2. Rebase on to linux-next tagged: next-20230310.
>>
>> v1:
>> https://lore.kernel.org/r/20221015055024.191855-1-mranostay@ti.com/
>>
>>  include/dt-bindings/mux/ti-serdes.h | 62 +++++++++++++++++++++++++++++
>>  1 file changed, 62 insertions(+)
>>
>> diff --git a/include/dt-bindings/mux/ti-serdes.h b/include/dt-bindings/mux/ti-serdes.h
>> index d3116c52ab72..669ca2d6abce 100644
>> --- a/include/dt-bindings/mux/ti-serdes.h
>> +++ b/include/dt-bindings/mux/ti-serdes.h
>> @@ -117,4 +117,66 @@
>>  #define J721S2_SERDES0_LANE3_USB		0x2
>>  #define J721S2_SERDES0_LANE3_IP4_UNUSED		0x3
>>  
>> +/* J784S4 */
>> +
>> +#define J784S4_SERDES0_LANE0_IP1_UNUSED		0x0
>> +#define J784S4_SERDES0_LANE0_PCIE1_LANE0	0x1

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