linux-kernel - Re: [PATCH v2 3/5] mtd: rawnand: qcom: Add support for param_page read exec

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <69bde397-9d6a-d6b2-846c-310fbbbaba98@quicinc.com>
Date:   Wed, 24 May 2023 14:58:55 +0530
From:   Md Sadre Alam <quic_mdalam@...cinc.com>
To:     Miquel Raynal <miquel.raynal@...tlin.com>
CC:     <mani@...nel.org>, <richard@....at>, <vigneshr@...com>,
        <linux-mtd@...ts.infradead.org>, <linux-arm-msm@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, <quic_srichara@...cinc.com>
Subject: Re: [PATCH v2 3/5] mtd: rawnand: qcom: Add support for param_page
 read exec_ops



On 5/22/2023 7:19 PM, Miquel Raynal wrote:
> Hi Md,
> 
> quic_mdalam@...cinc.com wrote on Thu, 11 May 2023 19:00:15 +0530:
> 
>> This change will add exec_ops for PARAM_PAGE_READ command.
>>
>> Co-developed-by: Sricharan Ramabadhran <quic_srichara@...cinc.com>
>> Signed-off-by: Sricharan Ramabadhran <quic_srichara@...cinc.com>
>> Signed-off-by: Md Sadre Alam <quic_mdalam@...cinc.com>
>> ---
>> Change in [v2]
>>
>> * Missed to post Cover-letter, so posting v2 patch with cover-letter
>>
>>   drivers/mtd/nand/raw/qcom_nandc.c | 91 ++++++++++++++++++++++++++++++-
>>   1 file changed, 90 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
>> index d2f2a8971907..8717d5086f80 100644
>> --- a/drivers/mtd/nand/raw/qcom_nandc.c
>> +++ b/drivers/mtd/nand/raw/qcom_nandc.c
>> @@ -3086,7 +3086,96 @@ static int qcom_erase_cmd_type_exec(struct nand_chip *chip, const struct nand_su
>>   
>>   static int qcom_param_page_type_exec(struct nand_chip *chip,  const struct nand_subop *subop)
>>   {
>> -	return 0;
>> +	struct qcom_nand_host *host = to_qcom_nand_host(chip);
>> +	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
>> +	struct qcom_op q_op;
>> +	const struct nand_op_instr *instr = NULL;
>> +	unsigned int op_id = 0;
>> +	unsigned int len = 0;
>> +	int ret = 0;
>> +
>> +	qcom_parse_instructions(chip, subop, &q_op);
>> +
>> +	q_op.cmd_reg |= PAGE_ACC | LAST_PAGE;
>> +
>> +	pre_command(host, NAND_CMD_PARAM);
>> +	/*
>> +	 * NAND_CMD_PARAM is called before we know much about the FLASH chip
>> +	 * in use. we configure the controller to perform a raw read of 512
>> +	 * bytes to read onfi params
> 
> There is no guess to do, just follow what the core asks.

   Sure, will fix this in next patch V3.
> 
>> +	 */
>> +	if (nandc->props->qpic_v2)
>> +		nandc_set_reg(chip, NAND_FLASH_CMD, q_op.cmd_reg);
>> +	else
>> +		nandc_set_reg(chip, NAND_FLASH_CMD, q_op.cmd_reg);
> 
> There is something wrong here.
> 
   Will fix this in next patch V3.

>> +
>> +	nandc_set_reg(chip, NAND_ADDR0, 0);
>> +	nandc_set_reg(chip, NAND_ADDR1, 0);
>> +	nandc_set_reg(chip, NAND_DEV0_CFG0, 0 << CW_PER_PAGE
>> +					| 512 << UD_SIZE_BYTES
>> +					| 5 << NUM_ADDR_CYCLES
>> +					| 0 << SPARE_SIZE_BYTES);
>> +	nandc_set_reg(chip, NAND_DEV0_CFG1, 7 << NAND_RECOVERY_CYCLES
>> +					| 0 << CS_ACTIVE_BSY
>> +					| 17 << BAD_BLOCK_BYTE_NUM
>> +					| 1 << BAD_BLOCK_IN_SPARE_AREA
>> +					| 2 << WR_RD_BSY_GAP
>> +					| 0 << WIDE_FLASH
>> +					| 1 << DEV0_CFG1_ECC_DISABLE);
>> +	if (!nandc->props->qpic_v2)
>> +		nandc_set_reg(chip, NAND_EBI2_ECC_BUF_CFG, 1 << ECC_CFG_ECC_DISABLE);
>> +
>> +	/* configure CMD1 and VLD for ONFI param probing in QPIC v1 */
>> +	if (!nandc->props->qpic_v2) {
>> +		nandc_set_reg(chip, NAND_DEV_CMD_VLD,
>> +			      (nandc->vld & ~READ_START_VLD));
>> +		nandc_set_reg(chip, NAND_DEV_CMD1,
>> +			      (nandc->cmd1 & ~(0xFF << READ_ADDR))
>> +			      | NAND_CMD_PARAM << READ_ADDR);
>> +	}
>> +
>> +	nandc_set_reg(chip, NAND_EXEC_CMD, 1);
>> +
>> +	if (!nandc->props->qpic_v2) {
>> +		nandc_set_reg(chip, NAND_DEV_CMD1_RESTORE, nandc->cmd1);
>> +		nandc_set_reg(chip, NAND_DEV_CMD_VLD_RESTORE, nandc->vld);
>> +	}
>> +
>> +	nandc_set_read_loc(chip, 0, 0, 0, 512, 1);
>> +
>> +	if (!nandc->props->qpic_v2) {
>> +		write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1, 0);
>> +		write_reg_dma(nandc, NAND_DEV_CMD1, 1, NAND_BAM_NEXT_SGL);
>> +	}
>> +
>> +	nandc->buf_count = 512;
> 
> The length is provided by the instruction.

    Will fix this in next patch V3.
> 
>> +	memset(nandc->data_buffer, 0xff, nandc->buf_count);
>> +
>> +	config_nand_single_cw_page_read(chip, false, 0);
>> +
>> +	read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
>> +		      nandc->buf_count, 0);
>> +
>> +	/* restore CMD1 and VLD regs */
>> +	if (!nandc->props->qpic_v2) {
>> +		write_reg_dma(nandc, NAND_DEV_CMD1_RESTORE, 1, 0);
>> +		write_reg_dma(nandc, NAND_DEV_CMD_VLD_RESTORE, 1, NAND_BAM_NEXT_SGL);
>> +	}
>> +
>> +	ret = submit_descs(nandc);
>> +	if (ret)
>> +		dev_err(nandc->dev, "failure in sbumitting param page descriptor\n");
>> +
>> +	free_descs(nandc);
>> +
>> +	ret = qcom_wait_rdy_poll(chip, q_op.rdy_timeout_ms);
>> +
>> +	instr = q_op.data_instr;
>> +	op_id = q_op.data_instr_idx;
>> +	len = nand_subop_get_data_len(subop, op_id);
>> +	memcpy(instr->ctx.data.buf.in, nandc->data_buffer, len);
>> +
>> +	return ret;
>>   }
>>   
>>   static int qcom_read_id_type_exec(struct nand_chip *chip, const struct nand_subop *subop)
> 
> 
> Thanks,
> Miquèl