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Message-ID: <20230525-upper-racing-a77b28c675f1@spud>
Date: Thu, 25 May 2023 22:55:16 +0100
From: Conor Dooley <conor@...nel.org>
To: Geert Uytterhoeven <geert+renesas@...der.be>
Cc: Thomas Gleixner <tglx@...utronix.de>,
Marc Zyngier <maz@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH] dt-bindings: interrupt-controller: sifive,plic: Sort
compatible values
On Thu, May 18, 2023 at 10:12:11PM +0100, Conor Dooley wrote:
> On Wed, May 10, 2023 at 03:26:00PM +0200, Geert Uytterhoeven wrote:
> > Restore alphabetical sort order of the supported SiFive-compatible
> > values.
> >
> > Signed-off-by: Geert Uytterhoeven <geert+renesas@...der.be>
>
> Palmer has assigned this one to me on the RISC-V patchwork, any objections
> to me taking it via the riscv-dt tree Marc? There's some other patches for
> a new platform that's almost ready touching the file too, so if you don't
> mind I'd like to grab this one.
Given the lack of objections, I've picked it up. Happy to drop again if
that's not okay.
Applied to riscv-dt-for-next, thanks!
[1/1] dt-bindings: timer: sifive,clint: Clean up compatible value section
https://git.kernel.org/conor/c/1bd2339df1b5
Thanks,
Conor.
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