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Message-ID: <ZG9FBgX2useVeuWl@surfacebook>
Date: Thu, 25 May 2023 14:22:46 +0300
From: andy.shevchenko@...il.com
To: Hugo Villeneuve <hugo@...ovil.com>
Cc: gregkh@...uxfoundation.org, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
jirislaby@...nel.org, jringle@...dpoint.com,
tomasz.mon@...lingroup.com, l.perczak@...lintechnologies.com,
linux-serial@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-gpio@...r.kernel.org,
Hugo Villeneuve <hvilleneuve@...onoff.com>
Subject: Re: [PATCH v3 09/11] serial: sc16is7xx: add I/O register translation
offset
Thu, May 25, 2023 at 12:03:23AM -0400, Hugo Villeneuve kirjoitti:
> From: Hugo Villeneuve <hvilleneuve@...onoff.com>
>
> If the shared GPIO pins on a dual port/channel variant like the
> SC16IS752 are configured as GPIOs for port A, and modem control lines
> on port A, we need to translate the Linux GPIO offset to an offset
> that is compatible with the I/O registers of the SC16IS7XX (IOState,
> IODir and IOIntEna).
>
> Add a new variable to store that offset and set it when we detect that
> special case.
...
> +/*
> + * We may need to translate the Linux GPIO offset to a SC16IS7XX offset.
> + * This is needed only for the case where a dual port variant is configured to
> + * have only port B as modem status lines.
> + *
> + * Example for SC16IS752/762 with upper bank (port A) set as GPIOs, and
> + * lower bank (port B) set as modem status lines (special case described above):
> + *
> + * Pin GPIO pin Linux GPIO SC16IS7XX
> + * name function offset offset
> + * --------------------------------------------------
> + * GPIO7/RIA GPIO7 3 7
> + * GPIO6/CDA GPIO6 2 6
> + * GPIO5/DTRA GPIO5 1 5
> + * GPIO4/DSRA GPIO4 0 4
> + * GPIO3/RIB RIB N/A N/A
> + * GPIO2/CDB CDB N/A N/A
> + * GPIO1/DTRB DTRB N/A N/A
> + * GPIO0/DSRB DSRB N/A N/A
> + *
> + * Example for SC16IS750/760 with upper bank (7..4) set as modem status lines,
Single space is enough.
> + * and lower bank (3..0) as GPIOs:
> + *
> + * Pin GPIO pin Linux GPIO SC16IS7XX
> + * name function offset offset
> + * --------------------------------------------------
> + * GPIO7/RI RI N/A N/A
> + * GPIO6/CD CD N/A N/A
> + * GPIO5/DTR DTR N/A N/A
> + * GPIO4/DSR DSR N/A N/A
> + * GPIO3 GPIO3 3 3
> + * GPIO2 GPIO2 2 2
> + * GPIO1 GPIO1 1 1
> + * GPIO0 GPIO0 0 0
> + */
Wondering if you can always register 8 pins and use valid mask to define which
one are in use?
--
With Best Regards,
Andy Shevchenko
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