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Message-ID: <0907fcc9-2ffd-df0c-2e4f-8d58ff393885@quicinc.com>
Date: Fri, 26 May 2023 11:58:26 +0530
From: Dikshita Agarwal <quic_dikshita@...cinc.com>
To: Konrad Dybcio <konrad.dybcio@...aro.org>,
Stanimir Varbanov <stanimir.k.varbanov@...il.com>,
Vikash Garodia <quic_vgarodia@...cinc.com>,
Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
"Mauro Carvalho Chehab" <mchehab@...nel.org>,
Dikshita Agarwal <dikshita@....qualcomm.com>,
Bryan O'Donoghue <bryan.odonoghue@...aro.org>,
Mansur Alisha Shaik <mansur@...eaurora.org>,
Jonathan Marek <jonathan@...ek.ca>,
Hans Verkuil <hans.verkuil@...co.com>
CC: Mauro Carvalho Chehab <mchehab+huawei@...nel.org>,
Stanimir Varbanov <stanimir.varbanov@...aro.org>,
<linux-media@...r.kernel.org>, <linux-arm-msm@...r.kernel.org>,
<linux-kernel@...r.kernel.org>,
"Marijn Suijten" <marijn.suijten@...ainline.org>
Subject: Re: [PATCH v3 07/17] media: venus: core: Assign registers based on
VPU version
On 5/18/2023 2:44 AM, Konrad Dybcio wrote:
> IRIS2(_1) has a different register map compared to other HFI6XX-
> using VPUs. AR50L uses the same offsets, but doesn't feature vbif_base
> and aon_base. Take care of it.
>
this patch now replaces V6 with corresponding/supported VPU versions
so update commit text accordingly.
- Dikshita
> Signed-off-by: Konrad Dybcio <konrad.dybcio@...aro.org>
> ---
> drivers/media/platform/qcom/venus/core.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/media/platform/qcom/venus/core.c b/drivers/media/platform/qcom/venus/core.c
> index 01671dd23888..69c77b2137cc 100644
> --- a/drivers/media/platform/qcom/venus/core.c
> +++ b/drivers/media/platform/qcom/venus/core.c
> @@ -246,7 +246,7 @@ static int venus_enumerate_codecs(struct venus_core *core, u32 type)
>
> static void venus_assign_register_offsets(struct venus_core *core)
> {
> - if (IS_V6(core)) {
> + if (IS_IRIS2(core) || IS_IRIS2_1(core)) {
> core->vbif_base = core->base + VBIF_BASE;
> core->cpu_base = core->base + CPU_BASE_V6;
> core->cpu_cs_base = core->base + CPU_CS_BASE_V6;
>
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