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Message-ID: <ZHD8ME66oRKzc-Kz@surfacebook>
Date: Fri, 26 May 2023 21:36:32 +0300
From: andy.shevchenko@...il.com
To: Hugo Villeneuve <hugo@...ovil.com>
Cc: andy.shevchenko@...il.com, gregkh@...uxfoundation.org,
robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
conor+dt@...nel.org, jirislaby@...nel.org, jringle@...dpoint.com,
tomasz.mon@...lingroup.com, l.perczak@...lintechnologies.com,
linux-serial@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-gpio@...r.kernel.org,
Hugo Villeneuve <hvilleneuve@...onoff.com>
Subject: Re: [PATCH v3 09/11] serial: sc16is7xx: add I/O register translation
offset
Thu, May 25, 2023 at 01:20:46PM -0400, Hugo Villeneuve kirjoitti:
> On Thu, 25 May 2023 11:31:45 -0400
> Hugo Villeneuve <hugo@...ovil.com> wrote:
> > On Thu, 25 May 2023 14:22:46 +0300
> > andy.shevchenko@...il.com wrote:
> > > Thu, May 25, 2023 at 12:03:23AM -0400, Hugo Villeneuve kirjoitti:
...
> > > Wondering if you can always register 8 pins and use valid mask to define which
> > > one are in use?
> >
> > I will look into it, I think it may be a good idea and could help to
> > simplify things a bit.
>
> finally, this was the way to go. The resulting code/patch is much simpler and
> elegant this way. Thank you for the suggestion.
>
> I will submit a V4 with all the changes.
Thank you for trying!
--
With Best Regards,
Andy Shevchenko
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