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Date: Mon, 29 May 2023 15:35:26 -0400
From: Hugo Villeneuve <hugo@...ovil.com>
To: Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>,
NXP Linux Team <linux-imx@....com>
Cc: hugo@...ovil.com, Hugo Villeneuve <hvilleneuve@...onoff.com>,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org
Subject: [PATCH] arm64: dts: imx8mn-var-som-symphony: adapt FEC pinctrl for SOMs with onboard PHY
From: Hugo Villeneuve <hvilleneuve@...onoff.com>
The VAR SOM symphony carrier board can be used with SOMs which have a
soldered ethernet PHY onboard and with SOMs which don't have one.
For SOMs with an onboard PHY, the PHY on the cartrier board is not
used, and GPIO1_IO9 is used as a reset line to the onboard PHY.
For SOMs without an onboard PHY, the PHY on the carrier board is
used. For this configuration, pca9534 GPIO 5 (located on the carrier
board) is used as a reset line to the PHY, and GPIO1_IO9 is not
used.
GPIO1_IO9 is not connected to any user-accessible pins or functions,
and leaving it enabled in the mux pinctrl for both configurations is
safe.
Signed-off-by: Hugo Villeneuve <hvilleneuve@...onoff.com>
---
.../dts/freescale/imx8mn-var-som-symphony.dts | 40 -------------------
1 file changed, 40 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts
index 3ed7021a487c..406a711486da 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts
@@ -152,46 +152,6 @@ &usbotg1 {
extcon = <&extcon_usbotg1>, <&extcon_usbotg1>;
};
-&pinctrl_fec1 {
- fsl,pins = <
- MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
- MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
- MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
- MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
- MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
- MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
- MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
- MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
- MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
- MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
- MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
- MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
- MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
- MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
- /* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */
- >;
-};
-
-&pinctrl_fec1_sleep {
- fsl,pins = <
- MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16 0x120
- MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17 0x120
- MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x120
- MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19 0x120
- MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20 0x120
- MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21 0x120
- MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x120
- MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x120
- MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27 0x120
- MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26 0x120
- MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23 0x120
- MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25 0x120
- MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x120
- MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x120
- /* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */
- >;
-};
-
&iomuxc {
pinctrl_captouch: captouchgrp {
fsl,pins = <
base-commit: 8b817fded42d8fe3a0eb47b1149d907851a3c942
--
2.30.2
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