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Message-ID: <CAFBinCCk6OziOxt2AY1A25C=9_pibhHsDK0wJNZ_AyHMd=z6SQ@mail.gmail.com>
Date:   Mon, 29 May 2023 22:41:31 +0200
From:   Martin Blumenstingl <martin.blumenstingl@...glemail.com>
To:     Старк Георгий Николаевич 
        <GNStark@...rdevices.ru>
Cc:     "jic23@...nel.org" <jic23@...nel.org>,
        Dmitry Rokosov <DDRokosov@...rdevices.ru>,
        "lars@...afoo.de" <lars@...afoo.de>,
        "neil.armstrong@...aro.org" <neil.armstrong@...aro.org>,
        "khilman@...libre.com" <khilman@...libre.com>,
        "jbrunet@...libre.com" <jbrunet@...libre.com>,
        "andy.shevchenko@...il.com" <andy.shevchenko@...il.com>,
        "nuno.sa@...log.com" <nuno.sa@...log.com>,
        "linux-iio@...r.kernel.org" <linux-iio@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-amlogic@...ts.infradead.org" 
        <linux-amlogic@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        kernel <kernel@...rdevices.ru>, Vyacheslav <adeep@...ina.in>
Subject: Re: [PATCH v1] meson saradc: fix clock divider mask length

Hi George,

On Mon, May 22, 2023 at 5:47 PM Старк Георгий Николаевич
<GNStark@...rdevices.ru> wrote:
>
> Hello Martin
>
> Actually you were right that my patch affects only meson8 family not the all new ones, my bad.
> It's clear from the driver code meson_saradc.c and dts files.
> I've made an experiment on a113l soc - changingclock_rate inmeson_sar_adc_param and measuring adc channel many times
> and with low clockfrequency (priv->adc_clk) time of measurementis high
> and vice versa. ADC_CLK_DIV field in SAR_ADC_REG3 is always zero.
Thanks for sharing your findings!

> I need to get s805 (meson8) board for example and made experiment on it.
If you don't find any Meson8 (S802)/Meson8b (S805) or Meson8m2 (S812)
board then please provide the code that you used for your experiment
as a patch so I can give it a try on my Odroid-C1 (Meson8b).


Best regards,
Martin

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