lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <cabc40f3-d1cb-bdd0-bd96-1a51cb861579@gmail.com>
Date:   Mon, 29 May 2023 18:08:56 +0200
From:   Matthias Brugger <matthias.bgg@...il.com>
To:     AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@...labora.com>
Cc:     robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
        conor+dt@...nel.org, weiyi.lu@...iatek.com, ikjn@...omium.org,
        chun-jie.chen@...iatek.com, tinghan.shen@...iatek.com,
        seiya.wang@...iatek.com, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-mediatek@...ts.infradead.org, kernel@...labora.com
Subject: Re: [PATCH 0/2] MT8192/95: Set correct MSDCPLL rate



On 22/05/2023 11:30, AngeloGioacchino Del Regno wrote:
> This series improves both stability/reliability and performance for
> eMMC and SD cards on MT8192 and MT8195, where the PLL may be set at
> a sub-optimal rate from the bootloader.
> 
> This was tested on MT8192 Asurada Spherion and MT8195 Cherry Tomato
> Chromebooks.
> 
> AngeloGioacchino Del Regno (2):
>    arm64: dts: mediatek: mt8192: Make sure MSDCPLL's rate is 400MHz
>    arm64: dts: mediatek: mt8195: Make sure MSDCPLL's rate is 400MHz
> 
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 ++
>   arch/arm64/boot/dts/mediatek/mt8195.dtsi | 2 ++
>   2 files changed, 4 insertions(+)
> 

Whole series applied, thanks a lot!
Matthias

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ