lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <80ec15f5-0c68-9076-020a-854720d84c8a@linaro.org>
Date:   Tue, 30 May 2023 17:38:42 +0200
From:   Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To:     Mao Jinlong <quic_jinlmao@...cinc.com>,
        Andy Gross <agross@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konrad.dybcio@...aro.org>,
        Suzuki K Poulose <suzuki.poulose@....com>,
        Mike Leach <mike.leach@...aro.org>,
        Leo Yan <leo.yan@...aro.org>, Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>
Cc:     coresight@...ts.linaro.org, linux-arm-kernel@...ts.infradead.org,
        linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org,
        devicetree@...r.kernel.org,
        Tingwei Zhang <quic_tingweiz@...cinc.com>,
        Yuanfang Zhang <quic_yuanfang@...cinc.com>,
        Tao Zhang <quic_taozha@...cinc.com>,
        Hao Zhang <quic_hazha@...cinc.com>
Subject: Re: [PATCH v1 3/3] dt-bindings: arm: Adds CoreSight CSR hardware
 definitions

On 26/05/2023 17:35, Mao Jinlong wrote:
> Adds new coresight-csr.yaml file describing the bindings required
> to define csr in the device trees.
> 
> Signed-off-by: Mao Jinlong <quic_jinlmao@...cinc.com>
> ---
>  .../bindings/arm/qcom,coresight-csr.yaml      | 62 +++++++++++++++++++
>  1 file changed, 62 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-csr.yaml
> 
> diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-csr.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-csr.yaml
> new file mode 100644
> index 000000000000..a79b4f6a8bdf
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-csr.yaml
> @@ -0,0 +1,62 @@
> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> +# Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/qcom,coresight-csr.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: CoreSight Slave Register - TPDA
> +
> +description: |
> +  CoreSight Slave Register block hosts miscellaneous configuration registers.
> +  Those configuration registers can be used to control, various coresight
> +  configurations.
> +
> +maintainers:
> +  - Mao Jinlong <quic_jinlmao@...cinc.com>
> +  - Hao Zhang <quic_hazha@...cinc.com>
> +
> +properties:
> +  $nodename:
> +    pattern: "^csr(@[0-9a-f]+)$"

Drop nodename, we do not enforce it for device schemas.

> +  compatible:
> +    items:
> +      - const: qcom,coresight-csr

Why qcom, not arm? Description and title suggests it is generic.

If it is SoC specific, then what is it exactly? IP block of SoC? Then it
would miss SoC specific compatibles.


> +
> +  reg:
> +    minItems: 1
> +    maxItems: 2

You need to describe the items

> +
> +  clocks:
> +    maxItems: 1
> +
> +  clock-names:
> +    items:
> +      - const: apb_pclk
> +
> +  qcom,set-byte-cntr-support:
> +    $ref: /schemas/types.yaml#/definitions/flag
> +    description:
> +      If set, indicates that CSR supports to set ETR_IRQ_CTRL register.

Why this cannot be deducted from SoC-specific compatible?

> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - clock-names
> +
> +additionalProperties: false
> +
> +examples:
> +  # minimum CSR definition.

Drop comment

> +  - |
> +    csr@...01000 {


Best regards,
Krzysztof

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ