Date:   Wed, 31 May 2023 00:42:39 +0300
From:   Andy Shevchenko <andy.shevchenko@...il.com>
To:     simon.guinot@...uanux.org
Cc:     Linus Walleij <linus.walleij@...aro.org>, xingtong_wu@....com,
        brgl@...ev.pl, linux-gpio@...r.kernel.org,
        linux-kernel@...r.kernel.org, henning.schild@...mens.com,
        xingtong.wu@...mens.com
Subject: Re: [PATCH v2 1/1] gpio-f7188x: fix base values conflicts with other
 gpio pins

On Tue, May 30, 2023 at 8:56 PM <simon.guinot@...uanux.org> wrote:
> On Tue, May 30, 2023 at 01:24:30AM +0300, andy.shevchenko@...il.com wrote:
> > Mon, May 29, 2023 at 03:54:36PM +0200, simon.guinot@...uanux.org kirjoitti:
> > > On Mon, May 29, 2023 at 03:03:28PM +0200, Linus Walleij wrote:
> > > > On Mon, May 29, 2023 at 2:27 PM <simon.guinot@...uanux.org> wrote:
> > > >
> > > > > It would be nice if a pin number found in the device datasheet could
> > > > > still be converted into a Linux GPIO number by adding the base of the
> > > > > first bank.
> > > >
> > > > We actively discourage this kind of mapping because of reasons stated
> > > > in drivers/gpio/TODO: we want dynamic number allocation to be the
> > > > norm.
> > >
> > > Sure but it would be nice to have a dynamic base applied to a controller
> > > (and not to each chip of this controller), and to respect the interval
> > > between the chips (as stated in the controllers datasheets).
> >
> > What you want is against the architecture. To fix this, you might change
> > the architecture of the driver to have one chip for the controller, but
> > it's quite questionable change. Also how can you guarantee ordering of
> > the enumeration? You probably need to *disable* SMP on the boot time.
> > This will still be fragile as long as GPIO chip can be unbound at run
> > time. Order can be changed.
> >
> > So, the patch is good and the correct way to go.
> >
> > P.S. The root cause is that hardware engineers and documentation writers
> > do not consider their hardware in the multi-tasking, multi-user general
> > purpose operating system, such as Linux. I believe the ideal fix is to fix the
> > documentation (datasheet).
>
> Some GPIO controllers (as Super-I/O) are multifunctional devices and
> pins are multiplexed. Some can be configured to act as GPIOs and some
> cannot. So there are holes. It is an hardware reality and not only an
> issue due to poorly written documents (even if there are issues with
> them too).

So, this is done with GPIO to pin mapping (and yes, pin control has to
be present). In simpler cases the valid mask is enough.

> Today we work around these holes by splitting the GPIOs between several
> chips.

What you are saying seems like a broken architecture of the certain
driver, i.e. exposing hardware not in the correct representation
(wrong mapping). Maybe I'm missing something...

> As a consequence "hardware" GPIO numbers don't exist in Linux. It
> requires some work from a user to first find the chip a GPIO belongs to
> and then compute the number. It is not terrible. But on some machines
> with a lot of GPIO controllers and chips it can be quite challenging
> (especially when ACPI is involved).

Not sure how ACPI makes things worse (except the number space used for
GpioIo() and GpioInt() resources, which in case of existing pin
control may be different to the pin numbering). In any case the pin
control case is covered nowadays in debugfs and one may look at that
to find the mapping and pin naming.

> I am only saying it would be nice for Linux users if they could use
> hardware GPIO numbers (i.e. as read in hardware documents).

It's impossible. I can make an example which is the UP board (or UP²
a.k.a. UP Square) where GPIO from SoC goes through CPLD and becomes
completely non-related in the documentation. AFAIU all the same for
Raspberry Pi.

Besides that, if a board has an I²C expander, and other I²C buses
available to connect anything, it will always be ambiguous.

-- 
With Best Regards,
Andy Shevchenko

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