| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <6452e00de4e446ddb25588e29fa9e768@exch03.asrmicro.com>
Date: Tue, 30 May 2023 06:07:21 +0000
From: Yan Zheng（严政） <zhengyan@...micro.com>
To: Marc Zyngier <maz@...nel.org>
CC: "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Gao Meitao（高玫涛）
<meitaogao@...micro.com>,
Zhou Qiao(周侨) <qiaozhou@...micro.com>,
"tglx@...utronix.de" <tglx@...utronix.de>,
Zhang Zhizhou(张治洲)
<zhizhouzhang@...micro.com>
Subject: RE: [PATCH v2] irqchip/gic-v3: workaround for ASR8601 when reading
mpidr
> -----Original Message-----
> From: Marc Zyngier [mailto:maz@...nel.org]
> Sent: Monday, May 29, 2023 11:02 PM
> To: Yan Zheng（严政） <zhengyan@...micro.com>
> Cc: linux-kernel@...r.kernel.org; Gao Meitao（高玫涛）
> <meitaogao@...micro.com>; Zhou Qiao(周侨) <qiaozhou@...micro.com>;
> tglx@...utronix.de; Zhang Zhizhou(张治洲) <zhizhouzhang@...micro.com>
> Subject: Re: [PATCH v2] irqchip/gic-v3: workaround for ASR8601 when reading
> mpidr
>
> On Mon, 22 May 2023 12:06:43 +0100,
> zhengyan <zhengyan@...micro.com> wrote:
> >
> > This patch add workaround for ASR8601, which uses an armv8.2 processor
> > with a gic-500. But gic-500 is incompatible with
> > ARMv8.2 implementations from ARM.
> >
> > ARMv8.2 from ARM implementation uses Multiprocessor Affinity Register
> > to identify the logical address of the core by
> > | cluster | core | thread |.
> > However, gic-500 only supports topologies with affinity levels less
> > than 2 as
> > | cluster | core|.
> >
> > So we need this patch as workaround to shift the MPIDR values to
> > ensure proper functionality
> >
> > Signed-off-by: zhengyan <zhengyan@...micro.com>
> > ---
> > Documentation/arm64/silicon-errata.rst | 4 ++++
> > drivers/irqchip/irq-gic-v3.c | 30
> ++++++++++++++++++++++++++
> > 2 files changed, 34 insertions(+)
> >
> > diff --git a/Documentation/arm64/silicon-errata.rst
> > b/Documentation/arm64/silicon-errata.rst
> > index 9e311bc43e05..d6430ade349d 100644
> > --- a/Documentation/arm64/silicon-errata.rst
> > +++ b/Documentation/arm64/silicon-errata.rst
> > @@ -214,3 +214,7 @@ stable kernels.
> > +----------------+-----------------+-----------------+-----------------------------+
> > | Fujitsu | A64FX | E#010001 |
> FUJITSU_ERRATUM_010001 |
> >
> > +----------------+-----------------+-----------------+----------------
> > -------------+
> > +
> > ++----------------+-----------------+-----------------+-----------------------------+
> > +| ASR | ASR8601 | #8601001 | N/A
> |
> > ++----------------+-----------------+-----------------+-----------------------------+
> > diff --git a/drivers/irqchip/irq-gic-v3.c
> > b/drivers/irqchip/irq-gic-v3.c index 6fcee221f201..cf64783dfe70 100644
> > --- a/drivers/irqchip/irq-gic-v3.c
> > +++ b/drivers/irqchip/irq-gic-v3.c
> > @@ -39,6 +39,9 @@
> >
> > #define FLAGS_WORKAROUND_GICR_WAKER_MSM8996 (1ULL << 0)
> > #define FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539 (1ULL << 1)
> > +#define FLAGS_WORKAROUND_ASR_ERRATUM_8601001 (1ULL << 2)
> > +
> > +#define ASR8601_AFF_QUIRK(aff) (aff >> 8)
>
> This is wrong. There are more than just affinity bits in MPIDR, and you're making
> a mess of the result.
>
Yes, I made a mistake here.
> >
> > #define GIC_IRQ_TYPE_PARTITION (GIC_IRQ_TYPE_LPI + 1)
> >
> > @@ -659,6 +662,9 @@ static u64 gic_mpidr_to_affinity(unsigned long
> > mpidr) {
> > u64 aff;
> >
> > + if (gic_data.flags & FLAGS_WORKAROUND_ASR_ERRATUM_8601001)
> > + mpidr = ASR8601_AFF_QUIRK(mpidr);
> > +
> > aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 |
> > MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
> > MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | @@ -970,6 +976,9
> @@
> > static int __gic_populate_rdist(struct redist_region *region, void __iomem
> *ptr)
> > * Convert affinity to a 32bit value that can be matched to
> > * GICR_TYPER bits [63:32].
> > */
> > + if (gic_data.flags & FLAGS_WORKAROUND_ASR_ERRATUM_8601001)
> > + mpidr = ASR8601_AFF_QUIRK(mpidr);
>
> It really wasn't what I had in mind when I asked you to place this inside a helper.
> The whole thing looks horrible, and I really don't want to have to maintain
> anything like it.
>
> I came up with the following patch, which keeps the workaround *in a single
> spot*.
>
> Let me know if that works for you.
>
> M.
>
Really thanks for your help, this patch works well for us.
My previous patch was too ugly, this one looks better. I didn't find this good solution.
Should I send a patch for v3, considering that you're the author?
> diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index
> 6fcee221f201..b7d69ef4da9f 100644
> --- a/drivers/irqchip/irq-gic-v3.c
> +++ b/drivers/irqchip/irq-gic-v3.c
> @@ -39,6 +39,7 @@
>
> #define FLAGS_WORKAROUND_GICR_WAKER_MSM8996 (1ULL << 0)
> #define FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539 (1ULL << 1)
> +#define FLAGS_WORKAROUND_ASR_ERRATUM_8601001 (1ULL << 2)
>
> #define GIC_IRQ_TYPE_PARTITION (GIC_IRQ_TYPE_LPI + 1)
>
> @@ -655,10 +656,16 @@ static int gic_irq_set_vcpu_affinity(struct irq_data *d,
> void *vcpu)
> return 0;
> }
>
> -static u64 gic_mpidr_to_affinity(unsigned long mpidr)
> +static u64 gic_cpu_to_affinity(int cpu)
> {
> + u64 mpidr = cpu_logical_map(cpu);
> u64 aff;
>
> + /* ASR8601 needs to have its affinities shifted down... */
> + if (unlikely(gic_data.flags &
> FLAGS_WORKAROUND_ASR_ERRATUM_8601001))
> + mpidr = (MPIDR_AFFINITY_LEVEL(mpidr, 1) |
> + (MPIDR_AFFINITY_LEVEL(mpidr, 2) << 8));
> +
> aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 |
> MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
> MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | @@ -913,7 +920,7
> @@ static void __init gic_dist_init(void)
> * Set all global interrupts to the boot CPU only. ARE must be
> * enabled.
> */
> - affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id()));
> + affinity = gic_cpu_to_affinity(smp_processor_id());
> for (i = 32; i < GIC_LINE_NR; i++)
> gic_write_irouter(affinity, base + GICD_IROUTER + i * 8);
>
> @@ -962,7 +969,7 @@ static int gic_iterate_rdists(int (*fn)(struct
> redist_region *, void __iomem *))
>
> static int __gic_populate_rdist(struct redist_region *region, void __iomem
> *ptr) {
> - unsigned long mpidr = cpu_logical_map(smp_processor_id());
> + unsigned long mpidr;
> u64 typer;
> u32 aff;
>
> @@ -970,6 +977,8 @@ static int __gic_populate_rdist(struct redist_region
> *region, void __iomem *ptr)
> * Convert affinity to a 32bit value that can be matched to
> * GICR_TYPER bits [63:32].
> */
> + mpidr = gic_cpu_to_affinity(smp_processor_id());
> +
> aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 |
> MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
> MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | @@ -1262,9 +1271,11
> @@ static u16 gic_compute_target_list(int *base_cpu, const struct cpumask
> *mask,
> unsigned long cluster_id)
> {
> int next_cpu, cpu = *base_cpu;
> - unsigned long mpidr = cpu_logical_map(cpu);
> + unsigned long mpidr;
> u16 tlist = 0;
>
> + mpidr = gic_cpu_to_affinity(cpu);
> +
> while (cpu < nr_cpu_ids) {
> tlist |= 1 << (mpidr & 0xf);
>
> @@ -1273,8 +1284,7 @@ static u16 gic_compute_target_list(int *base_cpu,
> const struct cpumask *mask,
> goto out;
> cpu = next_cpu;
>
> - mpidr = cpu_logical_map(cpu);
> -
> + mpidr = gic_cpu_to_affinity(cpu);
> if (cluster_id != MPIDR_TO_SGI_CLUSTER_ID(mpidr)) {
> cpu--;
> goto out;
> @@ -1318,7 +1328,7 @@ static void gic_ipi_send_mask(struct irq_data *d,
> const struct cpumask *mask)
> dsb(ishst);
>
> for_each_cpu(cpu, mask) {
> - u64 cluster_id = MPIDR_TO_SGI_CLUSTER_ID(cpu_logical_map(cpu));
> + u64 cluster_id =
> MPIDR_TO_SGI_CLUSTER_ID(gic_cpu_to_affinity(cpu));
> u16 tlist;
>
> tlist = gic_compute_target_list(&cpu, mask, cluster_id); @@ -1376,7
> +1386,7 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask
> *mask_val,
>
> offset = convert_offset_index(d, GICD_IROUTER, &index);
> reg = gic_dist_base(d) + offset + (index * 8);
> - val = gic_mpidr_to_affinity(cpu_logical_map(cpu));
> + val = gic_cpu_to_affinity(cpu);
>
> gic_write_irouter(val, reg);
>
> @@ -1786,6 +1796,15 @@ static bool gic_enable_quirk_nvidia_t241(void
> *data)
> return true;
> }
>
> +static bool gic_enable_quirk_asr8601(void *data) {
> + struct gic_chip_data *d = data;
> +
> + d->flags |= FLAGS_WORKAROUND_ASR_ERRATUM_8601001;
> +
> + return true;
> +}
> +
> static const struct gic_quirk gic_quirks[] = {
> {
> .desc = "GICv3: Qualcomm MSM8996 broken firmware",
> @@ -1823,6 +1842,11 @@ static const struct gic_quirk gic_quirks[] = {
> .mask = 0xffffffff,
> .init = gic_enable_quirk_nvidia_t241,
> },
> + {
> + .desc = "GICv3: ASR erratum 8601001",
> + .compatible = "asr,asr8601-gic-v3",
> + .init = gic_enable_quirk_asr8601,
> + },
> {
> }
> };
>
>
> --
> Without deviation from the norm, progress is not possible.
Powered by blists - more mailing lists