linux-kernel - Re: [PATCH v3 4/5] arm64: dts: mediatek: mt8192: Add thermal nodes and thermal zones

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Message-ID: <d50e3c7e-0900-7cb5-f6cc-ddc1f474ff33@collabora.com>
Date:   Tue, 30 May 2023 08:59:37 +0200
From:   AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@...labora.com>
To:     Bernhard Rosenkränzer <bero@...libre.com>,
        daniel.lezcano@...aro.org, rafael@...nel.org, amitk@...nel.org,
        rui.zhang@...el.com, matthias.bgg@...il.com, robh+dt@...nel.org,
        krzysztof.kozlowski+dt@...aro.org, rdunlap@...radead.org,
        ye.xingchen@....com.cn, p.zabel@...gutronix.de
Cc:     linux-pm@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org,
        linux-mediatek@...ts.infradead.org, devicetree@...r.kernel.org,
        wenst@...omium.org, james.lo@...iatek.com,
        rex-bc.chen@...iatek.com, nfraprado@...labora.com,
        abailon@...libre.com, amergnat@...libre.com, khilman@...libre.com
Subject: Re: [PATCH v3 4/5] arm64: dts: mediatek: mt8192: Add thermal nodes
 and thermal zones

Il 29/05/23 18:46, Bernhard Rosenkränzer ha scritto:
> From: Balsam CHIHI <bchihi@...libre.com>
> 
> Add thermal nodes and thermal zones for the mt8192.
> The mt8192 SoC has several hotspots around the CPUs.
> Specify the targeted temperature threshold to apply the mitigation
> and define the associated cooling devices.
> 
> Signed-off-by: Balsam CHIHI <bchihi@...libre.com>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@...labora.com>
> [bero@...libre.com: cosmetic changes]
> Signed-off-by: Bernhard Rosenkränzer <bero@...libre.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 454 +++++++++++++++++++++++
>   1 file changed, 454 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 5c30caf740265..330c5bb4ebc85 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -14,6 +14,8 @@
>   #include <dt-bindings/phy/phy.h>
>   #include <dt-bindings/power/mt8192-power.h>
>   #include <dt-bindings/reset/mt8192-resets.h>
> +#include <dt-bindings/thermal/thermal.h>
> +#include <dt-bindings/thermal/mediatek,lvts-thermal.h>
>   
>   / {
>   	compatible = "mediatek,mt8192";
> @@ -71,6 +73,7 @@ cpu0: cpu@0 {
>   			d-cache-sets = <128>;
>   			next-level-cache = <&l2_0>;
>   			capacity-dmips-mhz = <530>;
> +			#cooling-cells = <2>;
>   		};
>   
>   		cpu1: cpu@100 {
> @@ -88,6 +91,7 @@ cpu1: cpu@100 {
>   			d-cache-sets = <128>;
>   			next-level-cache = <&l2_0>;
>   			capacity-dmips-mhz = <530>;
> +			#cooling-cells = <2>;
>   		};
>   
>   		cpu2: cpu@200 {
> @@ -105,6 +109,7 @@ cpu2: cpu@200 {
>   			d-cache-sets = <128>;
>   			next-level-cache = <&l2_0>;
>   			capacity-dmips-mhz = <530>;
> +			#cooling-cells = <2>;
>   		};
>   
>   		cpu3: cpu@300 {
> @@ -122,6 +127,7 @@ cpu3: cpu@300 {
>   			d-cache-sets = <128>;
>   			next-level-cache = <&l2_0>;
>   			capacity-dmips-mhz = <530>;
> +			#cooling-cells = <2>;
>   		};
>   
>   		cpu4: cpu@400 {
> @@ -139,6 +145,7 @@ cpu4: cpu@400 {
>   			d-cache-sets = <256>;
>   			next-level-cache = <&l2_1>;
>   			capacity-dmips-mhz = <1024>;
> +			#cooling-cells = <2>;
>   		};
>   
>   		cpu5: cpu@500 {
> @@ -156,6 +163,7 @@ cpu5: cpu@500 {
>   			d-cache-sets = <256>;
>   			next-level-cache = <&l2_1>;
>   			capacity-dmips-mhz = <1024>;
> +			#cooling-cells = <2>;
>   		};
>   
>   		cpu6: cpu@600 {
> @@ -173,6 +181,7 @@ cpu6: cpu@600 {
>   			d-cache-sets = <256>;
>   			next-level-cache = <&l2_1>;
>   			capacity-dmips-mhz = <1024>;
> +			#cooling-cells = <2>;
>   		};
>   
>   		cpu7: cpu@700 {
> @@ -190,6 +199,7 @@ cpu7: cpu@700 {
>   			d-cache-sets = <256>;
>   			next-level-cache = <&l2_1>;
>   			capacity-dmips-mhz = <1024>;
> +			#cooling-cells = <2>;
>   		};
>   
>   		cpu-map {
> @@ -771,6 +781,17 @@ spi0: spi@...0a000 {
>   			status = "disabled";
>   		};
>   
> +		lvts_ap: thermal-sensor@...0b000 {
> +			compatible = "mediatek,mt8192-lvts-ap";
> +			reg = <0 0x1100b000 0 0x1000>;

reg = <0 0x1100b000 0 0xc00>;

...as 0xc00 should be more than sufficient. This is important for later
when we'll get SVS support up (which is in the LVTS-AP iospace range).

Regards,
Angelo