linux-kernel - Re: [PATCH V3] irqchip/gic-v3: Workaround Marvell erratum 38545 when reading IAR

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Message-ID: <CAMuHMdUmTV3Mmp-6LGiEqNG7DdxsBq-dpoGwTv7MHHMJQrGcLA@mail.gmail.com>
Date:   Tue, 30 May 2023 10:13:23 +0200
From:   Geert Uytterhoeven <geert@...ux-m68k.org>
To:     Will Deacon <will@...nel.org>
Cc:     catalin.marinas@....com, Linu Cherian <lcherian@...vell.com>,
        maz@...nel.org, tglx@...utronix.de, kernel-team@...roid.com,
        linuc.decode@...il.com, linux-arm-kernel@...ts.infradead.org,
        linux-kernel@...r.kernel.org,
        Linux-Renesas <linux-renesas-soc@...r.kernel.org>
Subject: Re: [PATCH V3] irqchip/gic-v3: Workaround Marvell erratum 38545 when
 reading IAR

Hi all,

On Mon, Mar 7, 2022 at 11:15 PM Will Deacon <will@...nel.org> wrote:
> On Mon, 7 Mar 2022 20:00:14 +0530, Linu Cherian wrote:
> > When a IAR register read races with a GIC interrupt RELEASE event,
> > GIC-CPU interface could wrongly return a valid INTID to the CPU
> > for an interrupt that is already released(non activated) instead of 0x3ff.
> >
> > As a side effect, an interrupt handler could run twice, once with
> > interrupt priority and then with idle priority.
> >
> > [...]
>
> Applied to arm64 (for-next/errata), thanks!
>
> [1/1] irqchip/gic-v3: Workaround Marvell erratum 38545 when reading IAR
>       https://git.kernel.org/arm64/c/24a147bcef8c

This workaround is now enabled on R-Car V4H:

    GIC: enabling workaround for GICv3: Cavium erratum 38539

which is not a Cavium SoC. Is this expected?
Thanks!

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds