linux-kernel - Re: [PATCH 1/2] MIPS: Allow MIPS32R2 kernel to run on P5600 and M5150

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <alpine.DEB.2.21.2305301011580.25569@angie.orcam.me.uk>
Date:   Tue, 30 May 2023 10:13:47 +0100 (BST)
From:   "Maciej W. Rozycki" <macro@...am.me.uk>
To:     Paul Cercueil <paul@...pouillou.net>
cc:     Jiaxun Yang <jiaxun.yang@...goat.com>, linux-mips@...r.kernel.org,
        linux-kernel@...r.kernel.org,
        Thomas Bogendoerfer <tsbogend@...ha.franken.de>
Subject: Re: [PATCH 1/2] MIPS: Allow MIPS32R2 kernel to run on P5600 and
 M5150

Hi Paul,

> >  I don't know why CPU_XBURST is also listed as both R1 and R2, the
> > history 
> > looks convoluted with no explanation.  Paul, is the CPU also dual-
> > revision 
> > or is it just a bug and it is supposed to be listed under one ISA
> > revision
> > only, presumably R2?
> 
> The XBurst CPU is R1 in older Ingenic SoCs (JZ4760B and older), and R2
> in newer SoCs (JZ4770 and newer).

 Great, thanks for confirming.  So the current arrangement is right and 
still we don't want to dual-list the P5600 or M5150.

  Maciej