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Message-ID: <fb3de5a5-4477-ec8d-eb2c-e00813f078a0@linaro.org>
Date: Wed, 31 May 2023 09:18:15 +0200
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Pranavi Somisetty <pranavi.somisetty@....com>, davem@...emloft.net,
edumazet@...gle.com, kuba@...nel.org, pabeni@...hat.com,
robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
nicolas.ferre@...rochip.com, claudiu.beznea@...rochip.com
Cc: git@....com, michal.simek@....com, harini.katakam@....com,
radhey.shyam.pandey@....com, netdev@...r.kernel.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org
Subject: Re: [PATCH net-next v3 1/2] dt-bindings: net: cdns,macb: Add
rx-watermark property
On 30/05/2023 11:51, Pranavi Somisetty wrote:
> watermark value is the minimum amount of packet data
> required to activate the forwarding process. The watermark
> implementation and maximum size is dependent on the device
> where Cadence MACB/GEM is used.
>
> Signed-off-by: Pranavi Somisetty <pranavi.somisetty@....com>
> ---
> Changes v2:
> None (patch added in v2)
>
> Changes v3:
> 1. Fixed DT schema error: "scalar properties shouldn't have array keywords".
> 2. Modified description of rx-watermark to include units of the watermark value.
> 3. Modified the DT property name corresponding to rx_watermark in
> pbuf_rxcutthru to "cdns,rx-watermark".
> 4. Modified commit description to remove references to Xilinx platforms,
> since the changes aren't platform specific.
> ---
> Documentation/devicetree/bindings/net/cdns,macb.yaml | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/net/cdns,macb.yaml b/Documentation/devicetree/bindings/net/cdns,macb.yaml
> index bef5e0f895be..2c733c061dce 100644
> --- a/Documentation/devicetree/bindings/net/cdns,macb.yaml
> +++ b/Documentation/devicetree/bindings/net/cdns,macb.yaml
> @@ -109,6 +109,14 @@ properties:
> power-domains:
> maxItems: 1
>
> + cdns,rx-watermark:
> + $ref: /schemas/types.yaml#/definitions/uint16
> + description:
> + Set watermark value for pbuf_rxcutthru reg and enable
> + rx partial store and forward. Watermark value here
> + corresponds to number of SRAM locations. The width of SRAM is
> + system dependent and can be 4,8 or 16 bytes.
You described device programming model - registers - not the actual
hardware.
Best regards,
Krzysztof
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