linux-kernel - Re: [PATCH] arm64/sysreg: Convert TRBE registers to automatic generation

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Date:   Wed, 31 May 2023 12:46:31 +0100
From:   Mark Brown <broonie@...nel.org>
To:     Anshuman Khandual <anshuman.khandual@....com>
Cc:     linux-arm-kernel@...ts.infradead.org,
        Catalin Marinas <catalin.marinas@....com>,
        Will Deacon <will@...nel.org>,
        Suzuki K Poulose <suzuki.poulose@....com>,
        Mike Leach <mike.leach@...aro.org>,
        Marc Zyngier <maz@...nel.org>, linux-kernel@...r.kernel.org,
        kvmarm@...ts.linux.dev, coresight@...ts.linaro.org
Subject: Re: [PATCH] arm64/sysreg: Convert TRBE registers to automatic
 generation

On Wed, May 31, 2023 at 11:25:24AM +0530, Anshuman Khandual wrote:

> This converts all TRBE related registers to automatic generation and update
> the driver as required. This does not cause any functional change.

>  arch/arm64/include/asm/el2_setup.h           |  2 +-
>  arch/arm64/include/asm/sysreg.h              | 49 ----------------
>  arch/arm64/kvm/debug.c                       |  2 +-
>  arch/arm64/kvm/hyp/nvhe/debug-sr.c           |  2 +-
>  arch/arm64/tools/sysreg                      | 59 ++++++++++++++++++++
>  drivers/hwtracing/coresight/coresight-trbe.c | 33 +++++------
>  drivers/hwtracing/coresight/coresight-trbe.h | 38 +++++--------
>  7 files changed, 94 insertions(+), 91 deletions(-)

These changes are easier to review if split up a bit, for example
separating the renames of constants from the actual conversion (and
doing different renames separately, though it looks like this only does
the addition of _EL1) or splitting things up by register so that the
registers that are OK don't need to be re-reviewed.

> +Sysreg	TRBLIMITR_EL1	3	0	9	11	0
> +Field	63:12	LIMIT
> +Res0	11:6

In DDI0601 2023-03 bit 6 is allocated to a field called XE.

> +Field	5	NVM

nVM.

> +Enum	4:3	TRIG_MODE
> +	0b00	STOP
> +	0b01	IRQ
> +	0b11	IGNR
> +EndEnum

This is documented as TM.

> +Enum	2:1	FILL_MODE
> +	0b00	FILL
> +	0b01	WRAP
> +	0b11	CBUF
> +EndEnum

This is documented as FM.

> +Field	0	ENABLE

This is documented as E.

> +Sysreg	TRBSR_EL1	3	0	9	11	3
> +Res0	63:32

In DDI0601 2023-03 MSS2 is allocated in this region from 55:32.

> +Field	31:26	EC
> +Res0	25:23

In DDI0601 2023-03 DAT is allocated in this region at bit 23.

> +Field	17	STOP

This is called S.

> +Res0	15:6
> +Field	5:0	BSC

In DDI0601 2023-03 bits 15:0 are a field MSS which has BSC allocated as
a subfield within it for some events, implementation defined events
could use a different encoding though.  We don't represent things like
this (or the various codes in ESR) within the scripting language yet.

> +Sysreg	TRBMAR_EL1	3	0	9	11	4
> +Res0	63:10
> +Field	9:8	SH
> +Field	7:0	ATTR
> +EndSysreg

DDI0601 2023-03 has a field PAS at bits 11:10.

> +Sysreg	TRBIDR_EL1	3	0	9	11	7
> +Res0	63:6

DDI0601 2023-03 has a field EA from bits 11:8.

> +Field	5	FLAG

This is documented as F.

> +Field	4	PROG

This is documented as P.

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