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Message-Id: <20230601030144.3458136-2-ilkka@os.amperecomputing.com>
Date: Wed, 31 May 2023 20:01:40 -0700
From: Ilkka Koskinen <ilkka@...amperecomputing.com>
To: Jonathan Corbet <corbet@....net>, Will Deacon <will@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Besar Wicaksono <bwicaksono@...dia.com>,
Suzuki K Poulose <suzuki.poulose@....com>,
Robin Murphy <robin.murphy@....com>
Cc: linux-doc@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
Ilkka Koskinen <ilkka@...amperecomputing.com>
Subject: [PATCH v2 1/5] perf: arm_cspmu: Support 32-bit accesses to 64-bit registers
Split the 64-bit register accesses if 64-bit access is not supported
by the PMU.
Signed-off-by: Ilkka Koskinen <ilkka@...amperecomputing.com>
---
drivers/perf/arm_cspmu/arm_cspmu.c | 8 ++++++--
drivers/perf/arm_cspmu/arm_cspmu.h | 1 +
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/perf/arm_cspmu/arm_cspmu.c b/drivers/perf/arm_cspmu/arm_cspmu.c
index a3f1c410b417..88547a2b73e6 100644
--- a/drivers/perf/arm_cspmu/arm_cspmu.c
+++ b/drivers/perf/arm_cspmu/arm_cspmu.c
@@ -701,8 +701,12 @@ static void arm_cspmu_write_counter(struct perf_event *event, u64 val)
if (use_64b_counter_reg(cspmu)) {
offset = counter_offset(sizeof(u64), event->hw.idx);
-
- writeq(val, cspmu->base1 + offset);
+ if (!cspmu->impl.split_64bit_access) {
+ writeq(val, cspmu->base1 + offset);
+ } else {
+ writel(lower_32_bits(val), cspmu->base1 + offset);
+ writel(upper_32_bits(val), cspmu->base1 + offset + 4);
+ }
} else {
offset = counter_offset(sizeof(u32), event->hw.idx);
diff --git a/drivers/perf/arm_cspmu/arm_cspmu.h b/drivers/perf/arm_cspmu/arm_cspmu.h
index 51323b175a4a..c0412cf2bd97 100644
--- a/drivers/perf/arm_cspmu/arm_cspmu.h
+++ b/drivers/perf/arm_cspmu/arm_cspmu.h
@@ -110,6 +110,7 @@ struct arm_cspmu_impl_ops {
/* Vendor/implementer descriptor. */
struct arm_cspmu_impl {
u32 pmiidr;
+ bool split_64bit_access;
struct arm_cspmu_impl_ops ops;
void *ctx;
};
--
2.40.1
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