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Message-Id: <20230601-topic-alpha_ctl-v1-0-b6a932dfcf68@linaro.org>
Date: Thu, 01 Jun 2023 11:39:06 +0200
From: Konrad Dybcio <konrad.dybcio@...aro.org>
To: Bjorn Andersson <andersson@...nel.org>,
Andy Gross <agross@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Iskren Chernev <me@...ren.info>
Cc: Marijn Suijten <marijn.suijten@...ainline.org>,
linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org,
Konrad Dybcio <konrad.dybcio@...aro.org>
Subject: [PATCH 0/2] Update parts of PLL_TEST_CTL(_U) if required
Some recent-ish clock drivers touching on the "standard" Alpha PLLs
have been specifying the values that should be written into the CTL
registers as mask-value combos, but that wasn't always reflected
properly (or at all). This series tries to fix that without affecitng
the drivers that actually provide the full register values.
Signed-off-by: Konrad Dybcio <konrad.dybcio@...aro.org>
---
Konrad Dybcio (2):
clk: qcom: clk-alpha-pll: Add a way to update some bits of test_ctl(_hi)
clk: qcom: gcc-sm6115: Add missing PLL config properties
drivers/clk/qcom/clk-alpha-pll.c | 19 +++++++++++++++----
drivers/clk/qcom/clk-alpha-pll.h | 2 ++
drivers/clk/qcom/gcc-sm6115.c | 8 ++++++++
3 files changed, 25 insertions(+), 4 deletions(-)
---
base-commit: 571d71e886a5edc89b4ea6d0fe6f445282938320
change-id: 20230601-topic-alpha_ctl-ab0dc0ad3654
Best regards,
--
Konrad Dybcio <konrad.dybcio@...aro.org>
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