linux-kernel - Re: [PATCH 0/2] Update parts of PLL_TEST_CTL(

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Message-ID: <9F5D5FD2-1D35-4EFF-B7A5-9459CB409309@iskren.info>
Date:   Fri, 02 Jun 2023 14:08:37 +0300
From:   Iskren Chernev <me@...ren.info>
To:     Konrad Dybcio <konrad.dybcio@...aro.org>,
        Bjorn Andersson <andersson@...nel.org>,
        Andy Gross <agross@...nel.org>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>
CC:     Marijn Suijten <marijn.suijten@...ainline.org>,
        linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH 0/2] Update parts of PLL_TEST_CTL(_U) if required



On June 1, 2023 12:39:06 PM GMT+03:00, Konrad Dybcio <konrad.dybcio@...aro.org> wrote:
>Some recent-ish clock drivers touching on the "standard" Alpha PLLs
>have been specifying the values that should be written into the CTL
>registers as mask-value combos, but that wasn't always reflected
>properly (or at all).

Yeah, that would be me. I didn't feel confident enough to add the mask parameter, but it seems very reasonable.

> This series tries to fix that without affecitng
>the drivers that actually provide the full register values.
>
>Signed-off-by: Konrad Dybcio <konrad.dybcio@...aro.org>

Reviewed-by: Iskren Chernev <me@...ren.info>

>---
>Konrad Dybcio (2):
>      clk: qcom: clk-alpha-pll: Add a way to update some bits of test_ctl(_hi)
>      clk: qcom: gcc-sm6115: Add missing PLL config properties
>
> drivers/clk/qcom/clk-alpha-pll.c | 19 +++++++++++++++----
> drivers/clk/qcom/clk-alpha-pll.h |  2 ++
> drivers/clk/qcom/gcc-sm6115.c    |  8 ++++++++
> 3 files changed, 25 insertions(+), 4 deletions(-)
>---
>base-commit: 571d71e886a5edc89b4ea6d0fe6f445282938320
>change-id: 20230601-topic-alpha_ctl-ab0dc0ad3654
>
>Best regards,