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Message-ID: <CAHp75Vcfa2cbACEPROuOptPM7c9SOp_TudK-4Rx45OhWPf=iiw@mail.gmail.com>
Date: Fri, 2 Jun 2023 16:11:21 +0300
From: Andy Shevchenko <andy.shevchenko@...il.com>
To: Sricharan Ramabadhran <quic_srichara@...cinc.com>
Cc: agross@...nel.org, andersson@...nel.org, konrad.dybcio@...aro.org,
robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
mturquette@...libre.com, sboyd@...nel.org, ulf.hansson@...aro.org,
linus.walleij@...aro.org, catalin.marinas@....com, will@...nel.org,
p.zabel@...gutronix.de, linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-mmc@...r.kernel.org, linux-gpio@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, robimarko@...il.com,
krzysztof.kozlowski@...aro.org
Subject: Re: [PATCH V8 2/8] clk: qcom: Add Global Clock controller (GCC)
driver for IPQ5018
On Fri, Jun 2, 2023 at 11:24 AM Sricharan Ramabadhran
<quic_srichara@...cinc.com> wrote:
>
> Add support for the global clock controller found on IPQ5018
> based devices.
...
> config IPQ_GCC_5332
> tristate "IPQ5332 Global Clock Controller"
> depends on ARM64 || COMPILE_TEST
> help
> Support for the global clock controller on ipq5332 devices.
> - Say Y if you want to use peripheral devices such as UART, SPI,
> - i2c, USB, SD/eMMC, etc.
Nothing in the commit message about this. Please, elaborate.
...
> +#include <linux/kernel.h>
> +#include <linux/err.h>
> +#include <linux/platform_device.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/clk-provider.h>
> +#include <linux/regmap.h>
> +#include <linux/reset-controller.h>
Why not keep this ordered?
Missing bits.h and maybe others, but in an unordered list it's harder to check.
...
> + &gpll4_main.clkr.hw
Can we keep trailing comma here and in similar cases, like
> + &ubi32_pll_main.clkr.hw
> + &gpll0_main.clkr.hw
(and many others)?
--
With Best Regards,
Andy Shevchenko
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