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Message-Id: <1685982557-28326-8-git-send-email-quic_rohiagar@quicinc.com>
Date: Mon, 5 Jun 2023 21:59:14 +0530
From: Rohit Agarwal <quic_rohiagar@...cinc.com>
To: agross@...nel.org, andersson@...nel.org, konrad.dybcio@...aro.org,
robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
conor+dt@...nel.org, rafael@...nel.org, viresh.kumar@...aro.org,
tglx@...utronix.de, maz@...nel.org, will@...nel.org,
robin.murphy@....com, joro@...tes.org, mani@...nel.org,
robimarko@...il.com
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-pm@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, iommu@...ts.linux.dev,
Imran Shaik <quic_imrashai@...cinc.com>,
Rohit Agarwal <quic_rohiagar@...cinc.com>
Subject: [PATCH v2 07/10] arm64: dts: qcom: Add support for GCC and RPMHCC for SDX75
From: Imran Shaik <quic_imrashai@...cinc.com>
Add support for GCC and RPMHCC clock nodes for SDX75 platform.
Signed-off-by: Imran Shaik <quic_imrashai@...cinc.com>
Signed-off-by: Rohit Agarwal <quic_rohiagar@...cinc.com>
---
arch/arm64/boot/dts/qcom/sdx75.dtsi | 37 ++++++++++++++++++++++++++++++++++++-
1 file changed, 36 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi
index 3d1646b..f83eef8 100644
--- a/arch/arm64/boot/dts/qcom/sdx75.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi
@@ -7,6 +7,7 @@
*/
#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,sdx75-gcc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
@@ -22,7 +23,21 @@
reg = <0 0x80000000 0 0>;
};
- clocks { };
+ clocks {
+ xo_board: xo_board {
+ compatible = "fixed-clock";
+ clock-frequency = <76800000>;
+ clock-output-names = "xo_board";
+ #clock-cells = <0>;
+ };
+
+ sleep_clk: sleep_clk {
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ clock-output-names = "sleep_clk";
+ #clock-cells = <0>;
+ };
+ };
cpus {
#address-cells = <2>;
@@ -358,6 +373,18 @@
ranges = <0 0 0 0 0x10 0>;
dma-ranges = <0 0 0 0 0x10 0>;
+ gcc: clock-controller@...00 {
+ compatible = "qcom,sdx75-gcc";
+ reg = <0x0 0x0080000 0x0 0x1f7400>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&sleep_clk>;
+ clock-names = "bi_tcxo",
+ "sleep_clk";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
tcsr_mutex: hwlock@...0000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x01f40000 0x0 0x40000>;
@@ -520,6 +547,14 @@
apps_bcm_voter: bcm_voter {
compatible = "qcom,bcm-voter";
};
+
+ rpmhcc: clock-controller {
+ compatible = "qcom,sdx75-rpmh-clk";
+ clocks = <&xo_board>;
+ clock-names = "xo";
+ #clock-cells = <1>;
+ };
+
};
};
--
2.7.4
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