linux-kernel - Re: [PATCH v2 08/10] arm64: dts: qcom: Add QUPv3 UART console node for SDX75

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Date:   Mon, 5 Jun 2023 20:17:27 +0200
From:   Konrad Dybcio <konrad.dybcio@...aro.org>
To:     Rohit Agarwal <quic_rohiagar@...cinc.com>, agross@...nel.org,
        andersson@...nel.org, robh+dt@...nel.org,
        krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
        rafael@...nel.org, viresh.kumar@...aro.org, tglx@...utronix.de,
        maz@...nel.org, will@...nel.org, robin.murphy@....com,
        joro@...tes.org, mani@...nel.org, robimarko@...il.com
Cc:     linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-pm@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, iommu@...ts.linux.dev
Subject: Re: [PATCH v2 08/10] arm64: dts: qcom: Add QUPv3 UART console node
 for SDX75



On 5.06.2023 18:29, Rohit Agarwal wrote:
> Add the debug uart console node in devicetree.
> 
> Signed-off-by: Rohit Agarwal <quic_rohiagar@...cinc.com>
> ---
>  arch/arm64/boot/dts/qcom/sdx75.dtsi | 49 +++++++++++++++++++++++++++++++++++++
>  1 file changed, 49 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi
> index f83eef8..47170ae 100644
> --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi
> @@ -385,6 +385,34 @@
>  			#power-domain-cells = <1>;
>  		};
>  
> +		qupv3_id_0: geniqup@...000 {
> +			compatible = "qcom,geni-se-qup";
> +			reg = <0x0 0x009c0000 0x0 0x2000>;
> +			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
> +				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
> +			clock-names = "m-ahb",
> +				      "s-ahb";
> +			iommus = <&apps_smmu 0xe3 0x0>;
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			ranges;
> +			status = "disabled";
> +
> +			uart1: serial@...000 {
> +				compatible = "qcom,geni-debug-uart";
> +				reg = <0x0 0x00984000 0x0 0x4000>;
> +				clock-names = "se";
> +				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
> +				interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
> +				pinctrl-0 = <&qupv3_se1_2uart_tx_active>,
> +					    <&qupv3_se1_2uart_rx_active>;
> +				pinctrl-1 = <&qupv3_se1_2uart_sleep>;
> +				pinctrl-names = "default",
> +						"sleep";
> +				status = "disabled";
> +			};
> +		};
> +
>  		tcsr_mutex: hwlock@...0000 {
>  			compatible = "qcom,tcsr-mutex";
>  			reg = <0x0 0x01f40000 0x0 0x40000>;
> @@ -413,6 +441,27 @@
>  			interrupt-controller;
>  			#interrupt-cells = <2>;
>  			wakeup-parent = <&pdc>;
> +
> +			qupv3_se1_2uart_tx_active: qupv3-se1-2uart-tx-active-state {
> +				pins = "gpio12";
> +				function = "qup_se1_l2_mira";
> +				drive-strength= <2>;
> +				bias-disable;
> +			};
You can bunch these two up like this:

qupv3_se1_2uart_active: qup.... {
	tx {
		pins = ...
		foo = ...
	};

	rx {
		pins = ...
		bar = ...
	};
};

Konrad
> +
> +			qupv3_se1_2uart_rx_active: qupv3-se1-2uart-rx-active-state {
> +				pins = "gpio13";
> +				function = "qup_se1_l3_mira";
> +				drive-strength= <2>;
> +				bias-disable;
> +			};
> +
> +			qupv3_se1_2uart_sleep: qupv3-se1-2uart-sleep-state {
> +				pins = "gpio12", "gpio13";
> +				function = "gpio";
> +				drive-strength = <2>;
> +				bias-pull-down;
> +			};
>  		};
>  
>  		apps_smmu: iommu@...00000 {