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Message-ID: <cc22f94e-eb51-89b4-d2a6-f56fff369ddd@quicinc.com>
Date: Mon, 5 Jun 2023 17:12:04 +0800
From: Tao Zhang <quic_taozha@...cinc.com>
To: Suzuki K Poulose <suzuki.poulose@....com>,
Mathieu Poirier <mathieu.poirier@...aro.org>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Konrad Dybcio <konradybcio@...il.com>,
Mike Leach <mike.leach@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>
CC: Jinlong Mao <quic_jinlmao@...cinc.com>,
Leo Yan <leo.yan@...aro.org>,
"Greg Kroah-Hartman" <gregkh@...uxfoundation.org>,
<coresight@...ts.linaro.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>,
Tingwei Zhang <quic_tingweiz@...cinc.com>,
Yuanfang Zhang <quic_yuanfang@...cinc.com>,
Trilok Soni <quic_tsoni@...cinc.com>,
Hao Zhang <quic_hazha@...cinc.com>,
<linux-arm-msm@...r.kernel.org>, <andersson@...nel.org>
Subject: Re: [PATCH v4 07/11] coresight-tpdm: Add nodes for dsb edge control
On 6/2/2023 5:00 PM, Suzuki K Poulose wrote:
> On 02/06/2023 09:45, Suzuki K Poulose wrote:
>> On 02/06/2023 09:21, Tao Zhang wrote:
>>>
>>> On 6/1/2023 8:14 PM, Suzuki K Poulose wrote:
>>>> On 27/04/2023 10:00, Tao Zhang wrote:
>>>>> Add the nodes to set value for DSB edge control and DSB edge
>>>>> control mask. Each DSB subunit TPDM has maximum of n(n<16) EDCR
>>>>> resgisters to configure edge control. DSB edge detection control
>>>>> 00: Rising edge detection
>>>>> 01: Falling edge detection
>>>>> 10: Rising and falling edge detection (toggle detection)
>>>>> And each DSB subunit TPDM has maximum of m(m<8) ECDMR registers to
>>>>> configure mask. Eight 32 bit registers providing DSB interface
>>>>> edge detection mask control.
>>>>>
>>>>> Signed-off-by: Tao Zhang <quic_taozha@...cinc.com>
>>>>> ---
>>>>> .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 32 +++++
>>>>> drivers/hwtracing/coresight/coresight-tpdm.c | 135
>>>>> ++++++++++++++++++++-
>>>>> drivers/hwtracing/coresight/coresight-tpdm.h | 21 ++++
>>>>> 3 files changed, 187 insertions(+), 1 deletion(-)
>>>>>
>>>>> diff --git
>>>>> a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
>>>>> b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
>>>>> index 348e167..a57f000 100644
>>>>> --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
>>>>> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
>>>>> @@ -60,3 +60,35 @@ Description:
>>>>> Bit[3] : Set to 0 for low performance mode.
>>>>> Set to 1 for high performance mode.
>>>>> Bit[4:8] : Select byte lane for high performance mode.
>>>>> +
>>>>> +What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge_ctrl
>>>>> +Date: March 2023
>>>>> +KernelVersion 6.3
>>>>> +Contact: Jinlong Mao (QUIC) <quic_jinlmao@...cinc.com>, Tao
>>>>> Zhang (QUIC) <quic_taozha@...cinc.com>
>>>>> +Description:
>>>>> + Read/Write a set of the edge control registers of the DSB
>>>>> + in TPDM.
>>>>> +
>>>>> + Expected format is the following:
>>>>> + <integer1> <integer2> <integer3>
>>>>> +
>>>>> + Where:
>>>>> + <integer1> : Start EDCR register number
>>>>> + <integer2> : End EDCR register number
>>>>> + <integer3> : The value need to be written
>>>>> +
>>>>> +What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge_ctrl_mask
>>>>> +Date: March 2023
>>>>> +KernelVersion 6.3
>>>>> +Contact: Jinlong Mao (QUIC) <quic_jinlmao@...cinc.com>, Tao
>>>>> Zhang (QUIC) <quic_taozha@...cinc.com>
>>>>> +Description:
>>>>> + Read/Write a set of the edge control mask registers of the
>>>>> + DSB in TPDM.
>>>>> +
>>>>> + Expected format is the following:
>>>>> + <integer1> <integer2> <integer3>
>>>>> +
>>>>> + Where:
>>>>> + <integer1> : Start EDCMR register number
>>>>> + <integer2> : End EDCMR register number
>>>>> + <integer3> : The value need to be written
>>>>> diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c
>>>>> b/drivers/hwtracing/coresight/coresight-tpdm.c
>>>>> index 1bacaa5..a40e458 100644
>>>>> --- a/drivers/hwtracing/coresight/coresight-tpdm.c
>>>>> +++ b/drivers/hwtracing/coresight/coresight-tpdm.c
>>>>> @@ -80,7 +80,14 @@ static void set_trigger_type(struct
>>>>> tpdm_drvdata *drvdata, u32 *val)
>>>>> static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata)
>>>>> {
>>>>> - u32 val;
>>>>> + u32 val, i;
>>>>> +
>>>>> + for (i = 0; i < TPDM_DSB_MAX_EDCR; i++)
>>>>> + writel_relaxed(drvdata->dsb->edge_ctrl[i],
>>>>> + drvdata->base + TPDM_DSB_EDCR(i));
>>>>> + for (i = 0; i < TPDM_DSB_MAX_EDCMR; i++)
>>>>> + writel_relaxed(drvdata->dsb->edge_ctrl_mask[i],
>>>>> + drvdata->base + TPDM_DSB_EDCMR(i));
>>>>
>>>> Do all TPDM DSBs have MAX_EDCR registers ? Or some have less than
>>>> that ?
>>>> If it is latter, do we need special care to avoid writing to
>>>> inexistent
>>>> registers ?
>>>>
>>> You are right, not all DSB TPDMs have MAX_EDCR registers. In our
>>> design, the inexistent register addresses
>>>
>>> are not occupied and safe for accessing.
>
> Does the TRM for the component say so ? Or is it by luck ? If the spec
> says it is RAZ/WriteIgnore, then we could keep the code as it is,
> with a comment. Otherwise, we could add a DT property. So please get
> this clarified with the H/W designers.
Confirmed with H/W designers, these addresses are reserved for the maximum
quantity of EDCR/EDCMR registers. It is safe to write data to them and
it will not
impact anything.
Best,
Tao
>
> Suzuki
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