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Message-ID: <723fd8bf-faa8-4c0a-13f7-222c33d62270@ti.com>
Date: Mon, 5 Jun 2023 21:36:29 +0530
From: "Verma, Achal" <a-verma1@...com>
To: Andrew Davis <afd@...com>, Nishanth Menon <nm@...com>,
Vignesh Raghavendra <vigneshr@...com>,
Tero Kristo <kristo@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Robert Nelson <robertcnelson@...il.com>
CC: <linux-arm-kernel@...ts.infradead.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 2/5] arm64: dts: ti: k3-j721e: Remove PCIe endpoint nodes
On 6/5/2023 8:47 PM, Andrew Davis wrote:
> On 6/5/23 9:54 AM, Verma, Achal wrote:
>>
>>
>> On 5/16/2023 9:57 PM, Andrew Davis wrote:
>>> On 5/16/23 11:22 AM, Verma, Achal wrote:
>>>>
>>>>
>>>> On 5/15/2023 10:51 PM, Andrew Davis wrote:
>>>>> These nodes are example nodes for the PCIe controller in "endpoint"
>>>>> mode.
>>>>> By default the controller is in "root complex" mode and there is
>>>>> already a
>>>>> DT node for the same.
>>>>>
>>>>> Examples should go in the bindings or other documentation.
>>>>>
>>>>> Remove this node.
>>>> How we will support EP from now onwards, using overlays ?
>>>>
>>>
>>> They are already disabled, how do you support them today?
>> As of now we edit the DTS (disable RC node and enable EP mode) but
>> now we have to delete RC node and add EP node and build DTBS which
>> looks like quite a work.
>>
>
> I'd argue having to use a different node with a different compatible
> to switch PCIe modes was not correct to begin with, it should have
> been a property flag. Or even better, the modes should have been
> switchable without modifying DTB at all.
>
> Since it was chosen to put hardware configuration in DT, you'll have
> to live with the problems that causes. My point it the same, examples
> of how to do something do not belong in the DT files. Put the example
> nodes in the documentation somewhere, then you can copy paste from that.
>
ok agree.
Later, have to device someway to make it quicker.
Thanks,
Achal Verma
> Andrew
>
>> Regards,
>> Achal Verma
>>
>>>
>>> Andrew
>>>
>>>> Regards,
>>>> Achal Verma
>>>>>
>>>>> Signed-off-by: Andrew Davis <afd@...com>
>>>>> ---
>>>>> .../boot/dts/ti/k3-j721e-beagleboneai64.dts | 24 ------
>>>>> .../dts/ti/k3-j721e-common-proc-board.dts | 25 ------
>>>>> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 82
>>>>> -------------------
>>>>> arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 24 ------
>>>>> 4 files changed, 155 deletions(-)
>>>>>
>>>>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
>>>>> b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
>>>>> index 8a62ac263b89..d77eeff0d81d 100644
>>>>> --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
>>>>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
>>>>> @@ -892,35 +892,11 @@ &pcie2_rc {
>>>>> status = "disabled";
>>>>> };
>>>>> -&pcie0_ep {
>>>>> - status = "disabled";
>>>>> - phys = <&serdes0_pcie_link>;
>>>>> - phy-names = "pcie-phy";
>>>>> - num-lanes = <1>;
>>>>> -};
>>>>> -
>>>>> -&pcie1_ep {
>>>>> - status = "disabled";
>>>>> - phys = <&serdes1_pcie_link>;
>>>>> - phy-names = "pcie-phy";
>>>>> - num-lanes = <2>;
>>>>> -};
>>>>> -
>>>>> -&pcie2_ep {
>>>>> - /* Unused */
>>>>> - status = "disabled";
>>>>> -};
>>>>> -
>>>>> &pcie3_rc {
>>>>> /* Unused */
>>>>> status = "disabled";
>>>>> };
>>>>> -&pcie3_ep {
>>>>> - /* Unused */
>>>>> - status = "disabled";
>>>>> -};
>>>>> -
>>>>> &icssg0_mdio {
>>>>> /* Unused */
>>>>> status = "disabled";
>>>>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
>>>>> b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
>>>>> index 7db0603125aa..87b7263f6547 100644
>>>>> --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
>>>>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
>>>>> @@ -840,35 +840,10 @@ &pcie2_rc {
>>>>> num-lanes = <2>;
>>>>> };
>>>>> -&pcie0_ep {
>>>>> - phys = <&serdes0_pcie_link>;
>>>>> - phy-names = "pcie-phy";
>>>>> - num-lanes = <1>;
>>>>> - status = "disabled";
>>>>> -};
>>>>> -
>>>>> -&pcie1_ep {
>>>>> - phys = <&serdes1_pcie_link>;
>>>>> - phy-names = "pcie-phy";
>>>>> - num-lanes = <2>;
>>>>> - status = "disabled";
>>>>> -};
>>>>> -
>>>>> -&pcie2_ep {
>>>>> - phys = <&serdes2_pcie_link>;
>>>>> - phy-names = "pcie-phy";
>>>>> - num-lanes = <2>;
>>>>> - status = "disabled";
>>>>> -};
>>>>> -
>>>>> &pcie3_rc {
>>>>> status = "disabled";
>>>>> };
>>>>> -&pcie3_ep {
>>>>> - status = "disabled";
>>>>> -};
>>>>> -
>>>>> &icssg0_mdio {
>>>>> status = "disabled";
>>>>> };
>>>>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>>>>> b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>>>>> index 10c8a5fb4ee2..e39f6d1e8d40 100644
>>>>> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>>>>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>>>>> @@ -816,26 +816,6 @@ pcie0_rc: pcie@...0000 {
>>>>> dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
>>>>> };
>>>>> - pcie0_ep: pcie-ep@...0000 {
>>>>> - compatible = "ti,j721e-pcie-ep";
>>>>> - reg = <0x00 0x02900000 0x00 0x1000>,
>>>>> - <0x00 0x02907000 0x00 0x400>,
>>>>> - <0x00 0x0d000000 0x00 0x00800000>,
>>>>> - <0x00 0x10000000 0x00 0x08000000>;
>>>>> - reg-names = "intd_cfg", "user_cfg", "reg", "mem";
>>>>> - interrupt-names = "link_state";
>>>>> - interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
>>>>> - ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
>>>>> - max-link-speed = <3>;
>>>>> - num-lanes = <2>;
>>>>> - power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
>>>>> - clocks = <&k3_clks 239 1>;
>>>>> - clock-names = "fck";
>>>>> - max-functions = /bits/ 8 <6>;
>>>>> - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
>>>>> - dma-coherent;
>>>>> - };
>>>>> -
>>>>> pcie1_rc: pcie@...0000 {
>>>>> compatible = "ti,j721e-pcie-host";
>>>>> reg = <0x00 0x02910000 0x00 0x1000>,
>>>>> @@ -864,26 +844,6 @@ pcie1_rc: pcie@...0000 {
>>>>> dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
>>>>> };
>>>>> - pcie1_ep: pcie-ep@...0000 {
>>>>> - compatible = "ti,j721e-pcie-ep";
>>>>> - reg = <0x00 0x02910000 0x00 0x1000>,
>>>>> - <0x00 0x02917000 0x00 0x400>,
>>>>> - <0x00 0x0d800000 0x00 0x00800000>,
>>>>> - <0x00 0x18000000 0x00 0x08000000>;
>>>>> - reg-names = "intd_cfg", "user_cfg", "reg", "mem";
>>>>> - interrupt-names = "link_state";
>>>>> - interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
>>>>> - ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
>>>>> - max-link-speed = <3>;
>>>>> - num-lanes = <2>;
>>>>> - power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
>>>>> - clocks = <&k3_clks 240 1>;
>>>>> - clock-names = "fck";
>>>>> - max-functions = /bits/ 8 <6>;
>>>>> - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
>>>>> - dma-coherent;
>>>>> - };
>>>>> -
>>>>> pcie2_rc: pcie@...0000 {
>>>>> compatible = "ti,j721e-pcie-host";
>>>>> reg = <0x00 0x02920000 0x00 0x1000>,
>>>>> @@ -912,26 +872,6 @@ pcie2_rc: pcie@...0000 {
>>>>> dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
>>>>> };
>>>>> - pcie2_ep: pcie-ep@...0000 {
>>>>> - compatible = "ti,j721e-pcie-ep";
>>>>> - reg = <0x00 0x02920000 0x00 0x1000>,
>>>>> - <0x00 0x02927000 0x00 0x400>,
>>>>> - <0x00 0x0e000000 0x00 0x00800000>,
>>>>> - <0x44 0x00000000 0x00 0x08000000>;
>>>>> - reg-names = "intd_cfg", "user_cfg", "reg", "mem";
>>>>> - interrupt-names = "link_state";
>>>>> - interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
>>>>> - ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
>>>>> - max-link-speed = <3>;
>>>>> - num-lanes = <2>;
>>>>> - power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
>>>>> - clocks = <&k3_clks 241 1>;
>>>>> - clock-names = "fck";
>>>>> - max-functions = /bits/ 8 <6>;
>>>>> - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
>>>>> - dma-coherent;
>>>>> - };
>>>>> -
>>>>> pcie3_rc: pcie@...0000 {
>>>>> compatible = "ti,j721e-pcie-host";
>>>>> reg = <0x00 0x02930000 0x00 0x1000>,
>>>>> @@ -960,28 +900,6 @@ pcie3_rc: pcie@...0000 {
>>>>> dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
>>>>> };
>>>>> - pcie3_ep: pcie-ep@...0000 {
>>>>> - compatible = "ti,j721e-pcie-ep";
>>>>> - reg = <0x00 0x02930000 0x00 0x1000>,
>>>>> - <0x00 0x02937000 0x00 0x400>,
>>>>> - <0x00 0x0e800000 0x00 0x00800000>,
>>>>> - <0x44 0x10000000 0x00 0x08000000>;
>>>>> - reg-names = "intd_cfg", "user_cfg", "reg", "mem";
>>>>> - interrupt-names = "link_state";
>>>>> - interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
>>>>> - ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
>>>>> - max-link-speed = <3>;
>>>>> - num-lanes = <2>;
>>>>> - power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
>>>>> - clocks = <&k3_clks 242 1>;
>>>>> - clock-names = "fck";
>>>>> - max-functions = /bits/ 8 <6>;
>>>>> - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
>>>>> - dma-coherent;
>>>>> - #address-cells = <2>;
>>>>> - #size-cells = <2>;
>>>>> - };
>>>>> -
>>>>> serdes_wiz4: wiz@...0000 {
>>>>> compatible = "ti,am64-wiz-10g";
>>>>> #address-cells = <1>;
>>>>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
>>>>> b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
>>>>> index f650a7fd66b4..07d3282a583b 100644
>>>>> --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
>>>>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
>>>>> @@ -896,35 +896,11 @@ &pcie2_rc {
>>>>> status = "disabled";
>>>>> };
>>>>> -&pcie0_ep {
>>>>> - status = "disabled";
>>>>> - phys = <&serdes0_pcie_link>;
>>>>> - phy-names = "pcie-phy";
>>>>> - num-lanes = <1>;
>>>>> -};
>>>>> -
>>>>> -&pcie1_ep {
>>>>> - status = "disabled";
>>>>> - phys = <&serdes1_pcie_link>;
>>>>> - phy-names = "pcie-phy";
>>>>> - num-lanes = <2>;
>>>>> -};
>>>>> -
>>>>> -&pcie2_ep {
>>>>> - /* Unused */
>>>>> - status = "disabled";
>>>>> -};
>>>>> -
>>>>> &pcie3_rc {
>>>>> /* Unused */
>>>>> status = "disabled";
>>>>> };
>>>>> -&pcie3_ep {
>>>>> - /* Unused */
>>>>> - status = "disabled";
>>>>> -};
>>>>> -
>>>>> &icssg0_mdio {
>>>>> status = "disabled";
>>>>> };
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