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Date: Tue, 6 Jun 2023 10:20:11 +0100
From: Catalin Marinas <catalin.marinas@....com>
To: Stephen Rothwell <sfr@...b.auug.org.au>
Cc: Christoffer Dall <cdall@...columbia.edu>,
Marc Zyngier <maz@...nel.org>, Will Deacon <will@...nel.org>,
Joey Gouly <joey.gouly@....com>,
Kristina Martsenko <kristina.martsenko@....com>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
Linux Next Mailing List <linux-next@...r.kernel.org>,
Oliver Upton <oliver.upton@...ux.dev>
Subject: Re: linux-next: manual merge of the kvm-arm tree with the arm64 tree
On Tue, Jun 06, 2023 at 11:49:27AM +1000, Stephen Rothwell wrote:
> diff --cc arch/arm64/kernel/cpufeature.c
> index a74f41c7280f,4a2ab3f366de..000000000000
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@@ -2662,35 -2641,17 +2662,46 @@@ static const struct arm64_cpu_capabilit
> .cpu_enable = cpu_enable_dit,
> ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, DIT, IMP)
> },
> + {
> + .desc = "Memory Copy and Memory Set instructions",
> + .capability = ARM64_HAS_MOPS,
> + .type = ARM64_CPUCAP_SYSTEM_FEATURE,
> + .matches = has_cpuid_feature,
> + .cpu_enable = cpu_enable_mops,
> + ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, MOPS, IMP)
> + },
> + {
> + .capability = ARM64_HAS_TCR2,
> + .type = ARM64_CPUCAP_SYSTEM_FEATURE,
> + .sys_reg = SYS_ID_AA64MMFR3_EL1,
> + .sign = FTR_UNSIGNED,
> + .field_pos = ID_AA64MMFR3_EL1_TCRX_SHIFT,
> + .field_width = 4,
> + .min_field_value = ID_AA64MMFR3_EL1_TCRX_IMP,
> + .matches = has_cpuid_feature,
> + },
> + {
> + .desc = "Stage-1 Permission Indirection Extension (S1PIE)",
> + .capability = ARM64_HAS_S1PIE,
> + .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
> + .sys_reg = SYS_ID_AA64MMFR3_EL1,
> + .sign = FTR_UNSIGNED,
> + .field_pos = ID_AA64MMFR3_EL1_S1PIE_SHIFT,
> + .field_width = 4,
> + .min_field_value = ID_AA64MMFR3_EL1_S1PIE_IMP,
> + .matches = has_cpuid_feature,
> + },
> + {
> + .desc = "Enhanced Virtualization Traps",
> + .capability = ARM64_HAS_EVT,
> + .type = ARM64_CPUCAP_SYSTEM_FEATURE,
> + .sys_reg = SYS_ID_AA64MMFR2_EL1,
> + .sign = FTR_UNSIGNED,
> + .field_pos = ID_AA64MMFR2_EL1_EVT_SHIFT,
> + .field_width = 4,
> + .min_field_value = ID_AA64MMFR2_EL1_EVT_IMP,
> + .matches = has_cpuid_feature,
> + },
> {},
> };
Thanks Stephen. It looks fine.
--
Catalin
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