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Message-ID: <688909b3-fb0a-1001-d38e-57dba23d3bae@amlogic.com>
Date: Wed, 7 Jun 2023 11:14:30 +0800
From: Liang Yang <liang.yang@...ogic.com>
To: Arseniy Krasnov <avkrasnov@...rdevices.ru>,
Miquel Raynal <miquel.raynal@...tlin.com>,
Richard Weinberger <richard@....at>,
Vignesh Raghavendra <vigneshr@...com>,
Neil Armstrong <neil.armstrong@...aro.org>,
Kevin Hilman <khilman@...libre.com>,
Jerome Brunet <jbrunet@...libre.com>,
Martin Blumenstingl <martin.blumenstingl@...glemail.com>
Cc: oxffffaa@...il.com, kernel@...rdevices.ru,
linux-mtd@...ts.infradead.org,
linux-arm-kernel@...ts.infradead.org,
linux-amlogic@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v1] mtd: rawnand: meson: waiting w/o wired ready/busy pin
Hi Arseniy,
On 2023/6/7 3:54, Arseniy Krasnov wrote:
> [ EXTERNAL EMAIL ]
>
> On 06.06.2023 22:51, Arseniy Krasnov wrote:
>> If there is no wired ready/busy pin, classic way to wait for command
>> completion is to use function 'nand_soft_waitrdy()'. Meson NAND has
>> special command which allows to wait for NAND_STATUS_READY bit without
>> reading status in a software loop (as 'nand_soft_waitrdy()' does). To
>> use it send this command along with NAND_CMD_STATUS, then wait for an
>> interrupt, and after interrupt send NAND_CMD_READ0. So this feature
>> allows to use interrupt driven waiting without wired ready/busy pin.
>>
>> Suggested-by: Liang Yang <liang.yang@...ogic.com>
>> Signed-off-by: Arseniy Krasnov <AVKrasnov@...rdevices.ru>
>> ---
>> drivers/mtd/nand/raw/meson_nand.c | 58 ++++++++++++++++++++++++++++++-
>> 1 file changed, 57 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/mtd/nand/raw/meson_nand.c b/drivers/mtd/nand/raw/meson_nand.c
>> index 074e14225c06..f4c5309a9527 100644
>> --- a/drivers/mtd/nand/raw/meson_nand.c
>> +++ b/drivers/mtd/nand/raw/meson_nand.c
>> @@ -38,6 +38,7 @@
>> #define NFC_CMD_SCRAMBLER_DISABLE 0
>> #define NFC_CMD_SHORTMODE_DISABLE 0
>> #define NFC_CMD_RB_INT BIT(14)
>> +#define NFC_CMD_RB_INT_NO_PIN ((0xb << 10) | BIT(18) | BIT(16))
>>
>> #define NFC_CMD_GET_SIZE(x) (((x) >> 22) & GENMASK(4, 0))
>>
>> @@ -94,6 +95,7 @@
>>
>> /* nand flash controller delay 3 ns */
>> #define NFC_DEFAULT_DELAY 3000
>> +#define NFC_NO_RB_PIN_DELAY 5
>>
>> #define ROW_ADDER(page, index) (((page) >> (8 * (index))) & 0xff)
>> #define MAX_CYCLE_ADDRS 5
>> @@ -179,6 +181,7 @@ struct meson_nfc {
>> u32 info_bytes;
>>
>> unsigned long assigned_cs;
>> + bool no_rb_pin;
>> };
>>
>> enum {
>> @@ -392,7 +395,41 @@ static void meson_nfc_set_data_oob(struct nand_chip *nand,
>> }
>> }
>>
>> -static int meson_nfc_queue_rb(struct meson_nfc *nfc, int timeout_ms)
>> +static int meson_nfc_wait_no_rb_pin(struct meson_nfc *nfc, int timeout_ms)
>> +{
>> + u32 cmd, cfg;
>> +
>> + meson_nfc_cmd_idle(nfc, nfc->timing.twb);
>> + meson_nfc_drain_cmd(nfc);
>> + meson_nfc_wait_cmd_finish(nfc, CMD_FIFO_EMPTY_TIMEOUT);
>> +
>> + cfg = readl(nfc->reg_base + NFC_REG_CFG);
>> + cfg |= NFC_RB_IRQ_EN;
>> + writel(cfg, nfc->reg_base + NFC_REG_CFG);
>> +
>> + reinit_completion(&nfc->completion);
>> + cmd = nfc->param.chip_select | NFC_CMD_CLE | NAND_CMD_STATUS;
>> + writel(cmd, nfc->reg_base + NFC_REG_CMD);
>> + meson_nfc_cmd_idle(nfc, NFC_NO_RB_PIN_DELAY);
>
> ^^^
>
>> +
>> + /* use the max erase time as the maximum clock for waiting R/B */
>> + cmd = NFC_CMD_RB | NFC_CMD_RB_INT_NO_PIN | nfc->timing.tbers_max;
>> + writel(cmd, nfc->reg_base + NFC_REG_CMD);
>> + meson_nfc_cmd_idle(nfc, NFC_NO_RB_PIN_DELAY);
>
> ^^^
> Liang, I've implemented "new RB_INT" way instead of 'nand_soft_waitrdy()'. There were two numbers
> 2 and 5 in 'meson_nfc_cmd_idle()' as time argument (here and above). I've replaced both with
> define of 5 == NFC_NO_RB_PIN_DELAY. Is it correct? 2 and 5 were from doc?
You can do like that. as i know, bigger has no impact.
yes, them come from the example code of the controller datasheet; but i
think we can delete them also.
>
> Thanks, Arseniy
>
>> +
>> + if (!wait_for_completion_timeout(&nfc->completion,
>> + msecs_to_jiffies(timeout_ms)))
>> + return -ETIMEDOUT;
>> +
>> + cmd = nfc->param.chip_select | NFC_CMD_CLE | NAND_CMD_READ0;
>> + writel(cmd, nfc->reg_base + NFC_REG_CMD);
>> + meson_nfc_drain_cmd(nfc);
>> + meson_nfc_wait_cmd_finish(nfc, CMD_FIFO_EMPTY_TIMEOUT);
>> +
>> + return 0;
>> +}
>> +
>> +static int meson_nfc_wait_rb_pin(struct meson_nfc *nfc, int timeout_ms)
>> {
>> u32 cmd, cfg;
>> int ret = 0;
>> @@ -420,6 +457,23 @@ static int meson_nfc_queue_rb(struct meson_nfc *nfc, int timeout_ms)
>> return ret;
>> }
>>
>> +static int meson_nfc_queue_rb(struct meson_nfc *nfc, int timeout_ms)
>> +{
>> + if (nfc->no_rb_pin) {
>> + /* This mode is used when there is no wired R/B pin.
>> + * It works like 'nand_soft_waitrdy()', but instead of
>> + * polling NAND_CMD_STATUS bit in the software loop,
>> + * it will wait for interrupt - controllers checks IO
>> + * bus and when it detects NAND_CMD_STATUS on it, it
>> + * raises interrupt. After interrupt, NAND_CMD_READ0 is
>> + * sent as terminator of the ready waiting procedure.
>> + */
>> + return meson_nfc_wait_no_rb_pin(nfc, timeout_ms);
>> + } else {
>> + return meson_nfc_wait_rb_pin(nfc, timeout_ms);
>> + }
>> +}
>> +
>> static void meson_nfc_set_user_byte(struct nand_chip *nand, u8 *oob_buf)
>> {
>> struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
>> @@ -1412,6 +1466,8 @@ static int meson_nfc_probe(struct platform_device *pdev)
>> return ret;
>> }
>>
>> + nfc->no_rb_pin = !of_property_read_bool(dev->of_node, "nand-rb");
>> +
>> writel(0, nfc->reg_base + NFC_REG_CFG);
>> ret = devm_request_irq(dev, irq, meson_nfc_irq, 0, dev_name(dev), nfc);
>> if (ret) {
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