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Message-ID: <20230607-helium-handler-5dc9616ebf2c@spud>
Date: Wed, 7 Jun 2023 18:40:40 +0100
From: Conor Dooley <conor@...nel.org>
To: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
Cc: Minda Chen <minda.chen@...rfivetech.com>,
Emil Renner Berthing <emil.renner.berthing@...onical.com>,
Vinod Koul <vkoul@...nel.org>,
Kishon Vijay Abraham I <kishon@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Pawel Laszczak <pawell@...ence.com>,
Peter Chen <peter.chen@...nel.org>,
Roger Quadros <rogerq@...nel.org>,
Philipp Zabel <p.zabel@...gutronix.de>,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-phy@...ts.infradead.org, linux-usb@...r.kernel.org,
linux-riscv@...ts.infradead.org,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Mason Huo <mason.huo@...rfivetech.com>
Subject: Re: [PATCH v6 7/7] riscv: dts: starfive: Add USB dts configuration
for JH7110
On Mon, May 29, 2023 at 03:46:21PM +0100, Greg Kroah-Hartman wrote:
> On Thu, May 25, 2023 at 10:36:38PM +0100, Conor Dooley wrote:
> > Greg,
> >
> > On Thu, May 18, 2023 at 07:27:50PM +0800, Minda Chen wrote:
> > > Add USB wrapper layer and Cadence USB3 controller dts
> > > configuration for StarFive JH7110 SoC and VisionFive2
> > > Board.
> > > USB controller connect to PHY, The PHY dts configuration
> > > are also added.
> > >
> > > Signed-off-by: Minda Chen <minda.chen@...rfivetech.com>
> >
> > > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > > index 71a8e9acbe55..b65f06c5b1b7 100644
> > > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > > @@ -366,6 +366,59 @@
> > > status = "disabled";
> > > };
> > >
> > > + usb0: usb@...00000 {
> > > + compatible = "starfive,jh7110-usb";
> > > + ranges = <0x0 0x0 0x10100000 0x100000>;
> > > + #address-cells = <1>;
> > > + #size-cells = <1>;
> > > + starfive,stg-syscon = <&stg_syscon 0x4>;
> > > + clocks = <&stgcrg JH7110_STGCLK_USB0_LPM>,
> >
> > Please don't pick this patch, if the rest of the series is applicable,
> > as this will break building the dtb as stgcrg does not yet exist in any
> > maintainer tree.
>
> Ok, I'll just take patch 6/7 then.
I think I missed this mail somehow. 5/7 had the binding for the driver
so probably that should've gone via the USB tree too?
Should apply on its own (no deps on the phy patches) & has dt-binding
maintainer reviews.
`b4 am -P 5 20230518112750.57924-6-minda.chen@...rfivetech.com` if
that's your cup of tea.
Cheers,
Conor.
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