linux-kernel - [PATCH v1 6/6] arm64: dts: meson: a1: add eMMC controller and its pins

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Message-ID: <20230607201641.20982-7-ddrokosov@sberdevices.ru>
Date:   Wed, 7 Jun 2023 23:16:41 +0300
From:   Dmitry Rokosov <ddrokosov@...rdevices.ru>
To:     <neil.armstrong@...aro.org>, <jbrunet@...libre.com>,
        <mturquette@...libre.com>, <sboyd@...nel.org>,
        <robh+dt@...nel.org>, <krzysztof.kozlowski+dt@...aro.org>,
        <khilman@...libre.com>, <martin.blumenstingl@...glemail.com>,
        <conor+dt@...nel.org>
CC:     <kernel@...rdevices.ru>, <sdfw_system_team@...rdevices.ru>,
        <rockosov@...il.com>, <linux-amlogic@...ts.infradead.org>,
        <linux-clk@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        Jan Dakinevich <yvdakinevich@...rdevices.ru>,
        Dmitry Rokosov <ddrokosov@...rdevices.ru>
Subject: [PATCH v1 6/6] arm64: dts: meson: a1: add eMMC controller and its pins

From: Jan Dakinevich <yvdakinevich@...rdevices.ru>

The definition is inspired by a similar one for AXG SoC family.
'sdio_pins' and 'sdio_clk_gate_pins' pinctrls are supposed to be used as
"default" and "clk-gate" in board-specific device trees.

'meson-gx' driver during initialization sets clock to safe low-frequency
value (400kHz). However, both source clocks ("clkin0" and "clkin1") are
high-frequency by default, and using of eMMC's internal divider is not
enough to achieve so low values. To provide low-frequency source,
reparent "sd_emmc_sel2" clock using 'assigned-clocks' property.

Signed-off-by: Jan Dakinevich <yvdakinevich@...rdevices.ru>
Signed-off-by: Dmitry Rokosov <ddrokosov@...rdevices.ru>
---
 arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 43 +++++++++++++++++++++++
 1 file changed, 43 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
index 3eb6aa9c00e0..a25170c61462 100644
--- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
@@ -134,6 +134,32 @@ mux {
 						bias-pull-down;
 					};
 				};
+
+				sdio_pins: sdio {
+					mux-0 {
+						groups = "sdcard_d0_x",
+							 "sdcard_d1_x",
+							 "sdcard_d2_x",
+							 "sdcard_d3_x",
+							 "sdcard_cmd_x";
+						function = "sdcard";
+						bias-pull-up;
+					};
+
+					mux-1 {
+						groups = "sdcard_clk_x";
+						function = "sdcard";
+						bias-disable;
+					};
+				};
+
+				sdio_clk_gate_pins: sdio_clk_gate {
+					mux {
+						groups = "sdcard_clk_x";
+						function = "sdcard";
+						bias-pull-down;
+					};
+				};
 			};
 
 			uart_AO: serial@...0 {
@@ -200,6 +226,23 @@ usb2_phy1: phy@...0 {
 				#phy-cells = <0>;
 				power-domains = <&pwrc PWRC_USB_ID>;
 			};
+
+			sd_emmc: sd@...00 {
+				compatible = "amlogic,meson-axg-mmc";
+				reg = <0x0 0x10000 0x0 0x800>;
+				interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clkc_periphs CLKID_SD_EMMC_A>,
+					 <&clkc_periphs CLKID_SD_EMMC>,
+					 <&clkc_pll CLKID_FCLK_DIV2>;
+				clock-names = "core",
+					      "clkin0",
+					      "clkin1";
+				assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_SEL2>;
+				assigned-clock-parents = <&xtal>;
+				resets = <&reset RESET_SD_EMMC_A>;
+				power-domains = <&pwrc PWRC_SD_EMMC_ID>;
+				status = "disabled";
+			};
 		};
 
 		gic: interrupt-controller@...01000 {
-- 
2.36.0