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Message-ID: <20230607080154.GA7545@wunner.de>
Date: Wed, 7 Jun 2023 10:01:54 +0200
From: Lukas Wunner <lukas@...ner.de>
To: Mario Limonciello <mario.limonciello@....com>
Cc: Bjorn Helgaas <bhelgaas@...gle.com>, linux-pci@...r.kernel.org,
linux-kernel@...r.kernel.org,
Mika Westerberg <mika.westerberg@...ux.intel.com>,
S-k Shyam-sundar <Shyam-sundar.S-k@....com>,
Natikar Basavaraj <Basavaraj.Natikar@....com>,
Deucher Alexander <Alexander.Deucher@....com>,
"Rafael J . Wysocki" <rafael@...nel.org>, linux-pm@...r.kernel.org,
Iain Lane <iain@...ngesquash.org.uk>,
Kuppuswamy Sathyanarayanan
<sathyanarayanan.kuppuswamy@...ux.intel.com>
Subject: Re: [PATCH v5 2/2] PCI: Don't assume root ports are power manageable
On Tue, May 30, 2023 at 11:39:47AM -0500, Mario Limonciello wrote:
> + /*
> + * It's not safe to put root ports that don't support power
> + * management into D3.
> + */
> + if (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT &&
> + !platform_pci_power_manageable(bridge))
> + return false;
> +
> /*
> * It should be safe to put PCIe ports from 2015 or newer
> * to D3.
My recollection is that we began suspending Root Ports to D3hot because
otherwise low power states of the whole CPU package could not be reached
on certain Intel CPUs from the 2015+ era.
Do we know if the DSDT of all those systems contains the required ACPI
objects to continue runtime suspending their Root Ports after this change?
Otherwise these systems would experience a power regression.
Thanks,
Lukas
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