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Message-ID: <636308462efb579734de829fb6e9cbda81b982f7.1686126439.git.quic_varada@quicinc.com>
Date:   Wed, 7 Jun 2023 16:26:09 +0530
From:   Varadarajan Narayanan <quic_varada@...cinc.com>
To:     <agross@...nel.org>, <andersson@...nel.org>,
        <konrad.dybcio@...aro.org>, <vkoul@...nel.org>,
        <kishon@...nel.org>, <robh+dt@...nel.org>,
        <krzysztof.kozlowski+dt@...aro.org>, <conor+dt@...nel.org>,
        <gregkh@...uxfoundation.org>, <catalin.marinas@....com>,
        <will@...nel.org>, <mturquette@...libre.com>, <sboyd@...nel.org>,
        <p.zabel@...gutronix.de>, <arnd@...db.de>,
        <geert+renesas@...der.be>, <neil.armstrong@...aro.org>,
        <nfraprado@...labora.com>, <broonie@...nel.org>,
        <rafal@...ecki.pl>, <quic_srichara@...cinc.com>,
        <quic_varada@...cinc.org>, <quic_wcheng@...cinc.com>,
        <linux-arm-msm@...r.kernel.org>, <linux-phy@...ts.infradead.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <linux-usb@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>, <linux-clk@...r.kernel.org>
CC:     Varadarajan Narayanan <quic_varada@...cinc.com>
Subject: [PATCH 5/9] phy: qcom-m31: Introduce qcom,m31 USB phy

Introduce CONFIG_PHY_QCOM_M31_USB for including the M31 phy driver

Signed-off-by: Varadarajan Narayanan <quic_varada@...cinc.com>
---
 drivers/phy/qualcomm/Kconfig | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig
index 67a45d9..8a363dd 100644
--- a/drivers/phy/qualcomm/Kconfig
+++ b/drivers/phy/qualcomm/Kconfig
@@ -188,3 +188,14 @@ config PHY_QCOM_IPQ806X_USB
 	  This option enables support for the Synopsis PHYs present inside the
 	  Qualcomm USB3.0 DWC3 controller on ipq806x SoC. This driver supports
 	  both HS and SS PHY controllers.
+
+config PHY_QCOM_M31_USB
+	tristate "Qualcomm M31 HS PHY driver support"
+	depends on (USB || USB_GADGET) && ARCH_QCOM
+	select USB_PHY
+	help
+	  Enable this to support M31 HS PHY transceivers on Qualcomm chips
+	  with DWC3 USB core. It handles PHY initialization, clock
+	  management required after resetting the hardware and power
+	  management. This driver is required even for peripheral only or
+	  host only mode configurations.
-- 
2.7.4

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