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Message-ID: <2d6d0012-7331-e2f9-dd97-ad661179b393@arm.com>
Date: Wed, 7 Jun 2023 12:09:32 +0100
From: Suzuki K Poulose <suzuki.poulose@....com>
To: Mike Leach <mike.leach@...aro.org>
Cc: coresight@...ts.linaro.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org,
Anshuman Khandual <anshuman.khandual@....com>,
Rob Herring <robh+dt@...nel.org>, frowand.list@...il.com,
linux@...linux.org.uk
Subject: Re: [PATCH] coresight: etm4x: Match all ETM4 instances based on
DEVARCH and DEVTYPE
On 07/06/2023 11:43, Mike Leach wrote:
> On Mon, 5 Jun 2023 at 14:30, Suzuki K Poulose <suzuki.poulose@....com> wrote:
>>
>> Instead of adding the PIDs forever to the list for the new CPUs, let us detect
>> a component to be ETMv4 based on the CoreSight CID, DEVTYPE=PE_TRACE and
>> DEVARCH=ETMv4. This is already done for some of the ETMs. We can extend the PID
>> matching to match the PIDR2:JEDEC, BIT[3], which must be 1 (RA0) always.
Fix RA0 => RAO
>>
>> Link: https://lkml.kernel.org/r/20230317030501.1811905-1-anshuman.khandual@arm.com
>> Cc: Anshuman Khandual <anshuman.khandual@....com>
>> Cc: Rob Herring <robh+dt@...nel.org>
>> Cc: frowand.list@...il.com
>> Cc: linux@...linux.org.uk
>> Cc: Mike Leach <mike.leach@...aro.org>
>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@....com>
>> +#define PIDR2_JEDEC BIT(3)
>> +#define PID_PIDR2_JEDEC (PIDR2_JEDEC << 16)
>> +/*
>> + * Match all PIDs in a given CoreSight device type and architecture, defined
>> + * by the uci.
>> + */
>> +#define CS_AMBA_MATCH_ALL_UCI(uci) \
>> + __CS_AMBA_UCI_ID(PID_PIDR2_JEDEC, PID_PIDR2_JEDEC, uci)
>>
>> /* extract the data value from a UCI structure given amba_id pointer. */
>> static inline void *coresight_get_uci_data(const struct amba_id *id)
>> --
>> 2.34.1
>>
> Reviewed by:- Mike Leach <mike.leach@...aro.org>
>
Thanks Mike, I have queued this, with the above fix:
[01] https://git.kernel.org/coresight/c/ab5ca6268afc
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