[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <CAPDyKFrq1U1R+tvz3WLZCv2m5ta09L1ozoV4w-H5w38qX91BKw@mail.gmail.com>
Date: Fri, 9 Jun 2023 00:47:40 +0200
From: Ulf Hansson <ulf.hansson@...aro.org>
To: Victor Shih <victorshihgli@...il.com>
Cc: adrian.hunter@...el.com, linux-mmc@...r.kernel.org,
linux-kernel@...r.kernel.org, benchuanggli@...il.com,
HL.Liu@...esyslogic.com.tw, Greg.tu@...esyslogic.com.tw,
Ben Chuang <ben.chuang@...esyslogic.com.tw>,
Victor Shih <victor.shih@...esyslogic.com.tw>
Subject: Re: [PATCH V5 2/4] mmc: sdhci-pci-gli: Set SDR104's clock to 205MHz
and enable SSC for GL9767
On Thu, 1 Jun 2023 at 03:51, Victor Shih <victorshihgli@...il.com> wrote:
>
> From: Victor Shih <victor.shih@...esyslogic.com.tw>
>
> Set GL9767 SDR104's clock to 205MHz and enable SSC feature
> depend on register 0x888 BIT(1).
>
> Signed-off-by: Ben Chuang <ben.chuang@...esyslogic.com.tw>
> Signed-off-by: Victor Shih <victor.shih@...esyslogic.com.tw>
> Acked-by: Adrian Hunter <adrian.hunter@...el.com>
> ---
> drivers/mmc/host/sdhci-pci-gli.c | 135 ++++++++++++++++++++++++++++++-
[...]
> +
> +static void gl9767_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 pdiv)
> +{
> + u32 pll;
> +
> + gl9767_vhs_write(pdev);
> +
> + pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll);
> + pll &= ~(PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV |
> + PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV |
> + PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN);
> + pll |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV, ldiv) |
> + FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV, pdiv) |
> + FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN, dir);
> + pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll);
> +
> + gl9767_vhs_read(pdev);
> +
> + /* wait for pll stable */
> + msleep(1);
According to Documentation/timers/timers-howto.rst, this should be
converted into usleep_range instead.
[...]
Other than the minor thing above, this looks good to me!
Kind regards
Uffe
Powered by blists - more mailing lists