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Message-ID: <20230609072906.2784594-5-wenst@chromium.org>
Date: Fri, 9 Jun 2023 15:29:05 +0800
From: Chen-Yu Tsai <wenst@...omium.org>
To: Matthias Brugger <matthias.bgg@...il.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>
Cc: Chen-Yu Tsai <wenst@...omium.org>, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>
Subject: [PATCH v2 4/4] arm64: dts: mediatek: mt8186: Wire up GPU voltage/frequency scaling
Add the GPU's OPP table. This is from the downstream ChromeOS kernel,
adapted to the new upstream opp-supported-hw binning format. Also add
dynamic-power-coefficient for the GPU.
Also add label for mfg1 power domain. This is to be used at the board
level to add a regulator supply for the power domain.
Signed-off-by: Chen-Yu Tsai <wenst@...omium.org>
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 140 ++++++++++++++++++++++-
1 file changed, 139 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index 3762a70ccafb..f04ae70c470a 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -647,6 +647,142 @@ clk32k: oscillator-32k {
clock-output-names = "clk32k";
};
+ gpu_opp_table: opp-table-gpu {
+ compatible = "operating-points-v2";
+
+ opp-299000000 {
+ opp-hz = /bits/ 64 <299000000>;
+ opp-microvolt = <612500>;
+ opp-supported-hw = <0xff>;
+ };
+
+ opp-332000000 {
+ opp-hz = /bits/ 64 <332000000>;
+ opp-microvolt = <625000>;
+ opp-supported-hw = <0xff>;
+ };
+
+ opp-366000000 {
+ opp-hz = /bits/ 64 <366000000>;
+ opp-microvolt = <637500>;
+ opp-supported-hw = <0xff>;
+ };
+
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <643750>;
+ opp-supported-hw = <0xff>;
+ };
+
+ opp-434000000 {
+ opp-hz = /bits/ 64 <434000000>;
+ opp-microvolt = <656250>;
+ opp-supported-hw = <0xff>;
+ };
+
+ opp-484000000 {
+ opp-hz = /bits/ 64 <484000000>;
+ opp-microvolt = <668750>;
+ opp-supported-hw = <0xff>;
+ };
+
+ opp-535000000 {
+ opp-hz = /bits/ 64 <535000000>;
+ opp-microvolt = <687500>;
+ opp-supported-hw = <0xff>;
+ };
+
+ opp-586000000 {
+ opp-hz = /bits/ 64 <586000000>;
+ opp-microvolt = <700000>;
+ opp-supported-hw = <0xff>;
+ };
+
+ opp-637000000 {
+ opp-hz = /bits/ 64 <637000000>;
+ opp-microvolt = <712500>;
+ opp-supported-hw = <0xff>;
+ };
+
+ opp-690000000 {
+ opp-hz = /bits/ 64 <690000000>;
+ opp-microvolt = <737500>;
+ opp-supported-hw = <0xff>;
+ };
+
+ opp-743000000 {
+ opp-hz = /bits/ 64 <743000000>;
+ opp-microvolt = <756250>;
+ opp-supported-hw = <0xff>;
+ };
+
+ opp-796000000 {
+ opp-hz = /bits/ 64 <796000000>;
+ opp-microvolt = <781250>;
+ opp-supported-hw = <0xff>;
+ };
+
+ opp-850000000 {
+ opp-hz = /bits/ 64 <850000000>;
+ opp-microvolt = <800000>;
+ opp-supported-hw = <0xff>;
+ };
+
+ opp-900000000-3 {
+ opp-hz = /bits/ 64 <900000000>;
+ opp-microvolt = <850000>;
+ opp-supported-hw = <0x8>;
+ };
+
+ opp-900000000-4 {
+ opp-hz = /bits/ 64 <900000000>;
+ opp-microvolt = <837500>;
+ opp-supported-hw = <0x10>;
+ };
+
+ opp-900000000-5 {
+ opp-hz = /bits/ 64 <900000000>;
+ opp-microvolt = <825000>;
+ opp-supported-hw = <0x30>;
+ };
+
+ opp-950000000-3 {
+ opp-hz = /bits/ 64 <950000000>;
+ opp-microvolt = <900000>;
+ opp-supported-hw = <0x8>;
+ };
+
+ opp-950000000-4 {
+ opp-hz = /bits/ 64 <950000000>;
+ opp-microvolt = <875000>;
+ opp-supported-hw = <0x10>;
+ };
+
+ opp-950000000-5 {
+ opp-hz = /bits/ 64 <950000000>;
+ opp-microvolt = <850000>;
+ opp-supported-hw = <0x30>;
+ };
+
+ opp-1000000000-3 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <950000>;
+ opp-supported-hw = <0x8>;
+ };
+
+ opp-1000000000-4 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <912500>;
+ opp-supported-hw = <0x10>;
+ };
+
+ opp-1000000000-5 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <875000>;
+ opp-supported-hw = <0x30>;
+ };
+ };
+
pmu-a55 {
compatible = "arm,cortex-a55-pmu";
interrupt-parent = <&gic>;
@@ -765,7 +901,7 @@ mfg0: power-domain@...186_POWER_DOMAIN_MFG0 {
#size-cells = <0>;
#power-domain-cells = <1>;
- power-domain@...186_POWER_DOMAIN_MFG1 {
+ mfg1: power-domain@...186_POWER_DOMAIN_MFG1 {
reg = <MT8186_POWER_DOMAIN_MFG1>;
mediatek,infracfg = <&infracfg_ao>;
#address-cells = <1>;
@@ -1558,6 +1694,8 @@ gpu: gpu@...40000 {
#cooling-cells = <2>;
nvmem-cells = <&gpu_speedbin>;
nvmem-cell-names = "speed-bin";
+ operating-points-v2 = <&gpu_opp_table>;
+ dynamic-power-coefficient = <4687>;
status = "disabled";
};
--
2.41.0.162.gfafddb0af9-goog
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