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Message-ID: <c1c34aa4-ac7d-2c07-bf92-05d887aed3d2@linaro.org>
Date:   Fri, 9 Jun 2023 11:07:18 +0200
From:   Konrad Dybcio <konrad.dybcio@...aro.org>
To:     Kathiravan T <quic_kathirav@...cinc.com>,
        Andy Gross <agross@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley <conor+dt@...nel.org>,
        linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH] arm64: dts: qcom: ipq9574: enable the SPI NOR support in
 RDP433



On 9.06.2023 10:15, Kathiravan T wrote:
> RDP433 has the support for SPI NOR, add the support for it.
> 
> Signed-off-by: Kathiravan T <quic_kathirav@...cinc.com>
> ---
> Note: This patch was part of initial submission
> https://lore.kernel.org/linux-arm-msm/20230329053726.14860-1-quic_kathirav@quicinc.com/
> however this got missed in between, so sending it across again.
> 
>  arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 21 +++++++++++++++++++++
>  1 file changed, 21 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
> index 2b3ed8d351f7..31ee19112157 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
> +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
> @@ -48,6 +48,20 @@
>  	};
>  };
>  
> +&blsp1_spi0 {
> +	pinctrl-0 = <&spi_0_pins>;
> +	pinctrl-names = "default";
> +	status = "okay";
> +
> +	flash@0 {
> +		compatible = "micron,n25q128a11", "jedec,spi-nor";
> +		reg = <0>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
If you're not adding a partition table, you can drop the address-
and size-cells properties, as they determine what the reg value of
the child looks like.

Konrad
> +		spi-max-frequency = <50000000>;
> +	};
> +};
> +
>  &sdhc_1 {
>  	pinctrl-0 = <&sdc_default_state>;
>  	pinctrl-names = "default";
> @@ -96,6 +110,13 @@
>  			bias-pull-down;
>  		};
>  	};
> +
> +	spi_0_pins: spi-0-state {
> +		pins = "gpio11", "gpio12", "gpio13", "gpio14";
> +		function = "blsp0_spi";
> +		drive-strength = <8>;
> +		bias-disable;
> +	};
>  };
>  
>  &xo_board_clk {

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