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Message-Id: <1686311249-6857-3-git-send-email-quic_krichai@quicinc.com>
Date: Fri, 9 Jun 2023 17:17:27 +0530
From: Krishna chaitanya chundru <quic_krichai@...cinc.com>
To: manivannan.sadhasivam@...aro.org
Cc: quic_vbadigan@...cinc.com, quic_ramkri@...cinc.com,
linux-arm-msm@...r.kernel.org,
Krishna chaitanya chundru <quic_krichai@...cinc.com>,
Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
devicetree@...r.kernel.org (open list:OPEN FIRMWARE AND FLATTENED
DEVICE TREE BINDINGS), linux-kernel@...r.kernel.org (open list)
Subject: [PATCH v3 2/3] arm: dts: qcom: sdx55: Add interconnect path
Add pcie-mem interconnect path to sdx55 target.
Signed-off-by: Krishna chaitanya chundru <quic_krichai@...cinc.com>
---
arch/arm/boot/dts/qcom-sdx55.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi
index 342c3d1..38943d4 100644
--- a/arch/arm/boot/dts/qcom-sdx55.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx55.dtsi
@@ -421,6 +421,10 @@
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "global",
"doorbell";
+
+ interconnects = <&system_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "pci-mem";
+
resets = <&gcc GCC_PCIE_BCR>;
reset-names = "core";
power-domains = <&gcc PCIE_GDSC>;
--
2.7.4
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