linux-kernel - [PATCH v1 4/6] dt-bindings: riscv: cpus: permit operating-points-v2

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Message-Id: <20230610-jacket-king-486b50a4e01d@spud>
Date:   Sat, 10 Jun 2023 18:24:51 +0100
From:   Conor Dooley <conor@...nel.org>
To:     palmer@...belt.com
Cc:     conor@...nel.org, Conor Dooley <conor.dooley@...rochip.com>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: [PATCH v1 4/6] dt-bindings: riscv: cpus: permit operating-points-v2

From: Conor Dooley <conor.dooley@...rochip.com>

To allow setting "unevaluatedProperties: false" for cpus.yaml, permit
the operating points property for RISC-V cpu nodes.

Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 9bf2b72a9460..00d1e273f1a9 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -108,6 +108,7 @@ properties:
   # RISC-V has multiple properties for cache op block sizes as the sizes
   # differ between individual CBO extensions
   cache-op-block-size: false
+  operating-points-v2: true
   # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
   timebase-frequency: false
 
-- 
2.39.2