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Message-Id: <20230610-purge-pretended-a0815886d300@spud>
Date:   Sat, 10 Jun 2023 18:24:49 +0100
From:   Conor Dooley <conor@...nel.org>
To:     palmer@...belt.com
Cc:     conor@...nel.org, Conor Dooley <conor.dooley@...rochip.com>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: [PATCH v1 2/6] dt-bindings: riscv: cpus: allow clocks property

From: Conor Dooley <conor.dooley@...rochip.com>

Having disallowed additionalProperties, dtbs_check complains about
unevaluated clocks properties. Permit a single clock, as that's all any
current dts uses.

Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index e89a10d9c06b..3808a6703b2d 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -58,6 +58,9 @@ properties:
       Identifies that the hart uses the RISC-V instruction set
       and identifies the type of the hart.
 
+  clocks:
+    maxItems: 1
+
   mmu-type:
     description:
       Identifies the MMU address translation mode used on this
-- 
2.39.2

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