[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <20230610-koala-bronze-3592637a5d1f@spud>
Date: Sat, 10 Jun 2023 18:24:53 +0100
From: Conor Dooley <conor@...nel.org>
To: palmer@...belt.com
Cc: conor@...nel.org, Conor Dooley <conor.dooley@...rochip.com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: [PATCH v1 6/6] dt-bindings: riscv: cpus: switch to unevaluatedProperties: false
From: Conor Dooley <conor.dooley@...rochip.com>
To permit validation of cpu nodes, swap "additionalProperties: true"
out for "unevaluatedProperties: false".
Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 5e2db35411f1..d82d5c872a0e 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -152,7 +152,7 @@ required:
- riscv,isa
- interrupt-controller
-additionalProperties: true
+unevaluatedProperties: false
examples:
- |
--
2.39.2
Powered by blists - more mailing lists